ModelBest ForgeKernel Surpasses DeepSeek FlashMLA by 9.8% in Live Operator-Writing Session and Goes Open Source

No source code, no paper, starting directly from zero.

Just this morning, ForgeKernel, an Agent with no human involvement, and without needing to reference DeepSeek's original implementation, wrote DeepSeek's latest core operator 9.8% faster in front of the entire internet!

And the entire process was livestreamed, taking only 22.5 hours (from the perspective of designing operators, that's a short amount of time), and it also drew quite a few netizens to watch:

Specifically, the content of this livestream was an Agent, on an NVIDIA B200, surpassing DeepSeek-V4.1's FlashMLA Prefill operator.

FlashMLA is the attention core operator library open-sourced by DeepSeek, and DeepInfer, the inference framework just open-sourced on October 20, has also integrated it; it comes from the hands of a team widely recognized in the industry as the strongest in Infra, and can be said to represent the pinnacle of human hand-written operators. And as we just said, all the AI received was the operator's mathematical definition and the target hardware constraints; it had to start from zero frames and improve round after round through self-evolution.

During these 22.5 hours, every rewrite and every jump in performance numbers was laid out, fresh and clear, before the eyes of the entire audience:

42 rounds of iteration throughout, leaving 32 versions, using 1 B200 and 22 GPU hours; and the code humans wrote for this operator was 0 lines.

The pinnacle of hand-writing was thus surpassed by an operator for which humans did not write a single line of code.

So what kind of Agent is this?

It is ForgeKernel, the operator generation system from ModelBest; and after this livestream ended, the Intelligent Evolution Lab immediately joined forces with the OpenBMB community to announce it was open source.

On October 27, Ascend CANN officially posted, and "named" ForgeKernel—

At the same time, it topped all three major hardware leaderboards: CANNBench 950DT, 950PR, and A3!

These three leaderboards correspond to three types of Ascend hardware, and the highlights of their results can be said to differ in each case.

Let's first look at the 950DT leaderboard, which is also the one among the three where the economic calculation is most obvious.

On this leaderboard, ForgeKernel ranks first with 4,010.75 points, leading the second place by 27.8%; the baseline speedup is 1.533×, about 143% of the second place.

This means that under the same hardware investment, usable computing power increases by nearly 50%, and enterprises' computing power procurement and deployment costs can be reduced by about half accordingly.

What makes this leaderboard worth noting is that 950DT is a new-generation chip, and its supporting operator library is still in the early stages of construction, with a long manual adaptation cycle, yet ForgeKernel was the first to complete adaptation and reach the top.

950PR is the most fiercely competitive of the three leaderboards, with the top three all reaching a baseline speedup of 1.3×:

On this leaderboard, ForgeKernel has a total score of 4,165.94, also ranking first; the baseline speedup is 1.638×, about 1.18 times that of the second place.

Finally, there is A3, which is the currently widely used Ascend 910C.

As early as CANNBench v1.1, which closed its leaderboard on October 15, it had already taken first place on the A3 hardware leaderboard; after v2.0 opened, it has never given up this position, with a current total score of 4,341.16 and a baseline speedup of 1.898×, about 1.22 times that of the second place.

In this livestream, ForgeKernel ran on an NVIDIA B200 using CUDA, an ecosystem that has accumulated years of expert experience; while these three leaderboards were run on Ascend, which has its own independent architecture and toolchain.

Although the software and hardware on the two sides differ greatly, ForgeKernel was able to use the same system to take first place on both sides.

So the next question is, how did it do it?

How fast a model can ultimately run depends to a large extent on the operators.

Because for the same model and the same chip, swapping in a more efficient set of operators will create an obvious performance gap.

For a long time, high-performance operators have relied on senior engineers to hand-write and tune them one by one, with long cycles and high barriers. The CUDA ecosystem has reached where it is today thanks to years of expert accumulation; while for domestic chips, every time a new generation of hardware comes out or a new model arrives, adaptation must be done all over again.

In a word, the number of human experts cannot keep up with the iteration speed of chips and models.

So how can this situation be cracked?

On October 27, the ForgeKernel team and institutions including Tsinghua University published a paper on arXiv titled JustGoal: With Only a Goal, the AI Baseline Is Above the Expert Kernels.

In this paper, the research team gave the model only an optimization goal, provided no operator knowledge, and did not prescribe a fixed process, letting it write on its own. As a result, on the B200, the model beat the human-maintained open-source library on 8 of 10 operators.

They also put the same model under the dedicated framework KDA-0.5, developed with the participation of the MIT team led by Han Song, and its average score on single-configuration optimization tasks was only 0.95× that of JustGoal. In other words, writing operators increasingly depends on the model's own capabilities, and the experience and processes pre-written by experts are playing a smaller role.

However, giving only the goal also has its limitations. The model is good at tuning details, but it struggles to independently design a good overall architecture, and it often locks in its route within the first few attempts at the start, after which it can only fine-tune within the original architecture. ForgeKernel is built on top of JustGoal specifically to fill this gap.

Its approach can be divided into three parts:

And these three parts happen to correspond one-to-one with the livestream we just showed.

ForgeKernel first surpassed its own previous-generation version, and only then surpassed FlashMLA—this is self-evolution.

In the later stages, it also discovered on its own that Q's burst loading was competing with KV data movement for memory access resources, so it proactively controlled the pacing of Q requests, cutting another 2.4% off the runtime—a judgment that used to require a senior expert.

Across more operators, ForgeKernel matched or surpassed expert implementations in 24 of 29 comparisons, and it also matched or surpassed all 7 strongest operators publicly released by three leading Agent systems.

These gains can also be replicated across different domestic chips, because ForgeKernel's design has another advantage for domestic chips: it does not depend on any specific piece of hardware.

Concrete operator implementations must be written closely around each chip's hardware characteristics and cannot be copied directly; but the method by which ForgeKernel organizes optimization is general and does not preset a fixed process for any chip. Switching from Nvidia to Ascend, it only needs to change the performance analysis tool from NCU to msprof, and the hardware knowledge required by the new chip is then accumulated by the model through testing on that chip.

As a result, ForgeKernel can be quickly migrated to other domestic chips, and when a new generation of domestic chips is released, there is no need to build a new adaptation process from scratch.

If an operator can be 1% faster, what exactly does that mean?

According to the latest Gartner forecast, global AI infrastructure spending in 2026 will be about $1.48 trillion. At that scale, every 1% improvement in computing efficiency corresponds to about $14.8 billion.

On domestic chips, this calculation becomes even more pronounced.

Nvidia's CUDA has been optimized by experts for years, and there are many ready-made high-performance operators, so there is limited room for AI to speed things up further; the operator libraries that accompany domestic chips are still incomplete, and many operators have not been fully tuned, so the gains AI can bring are more obvious.

When the ForgeKernel team used AI to optimize training frameworks, they also saw this difference: the same approach can deliver a 20%–30% speedup on domestic chips, versus 5%–10% on Nvidia, which means ForgeKernel can further improve the cost-effectiveness of domestic chips in training and inference tasks and narrow the gap with Nvidia.

In fact, these operators that surpass human experts have not remained on the leaderboards; they have already moved into real industrial frontline use.

At present, operators generated by ForgeKernel have been officially integrated into the training framework, and long-training tests of MiniCPM5-1B have been completed on domestic chips and the Nvidia platform.

More notably, in this reconstruction of the computing foundation, domestic large models represented by DeepSeek V4.1 have already begun to participate in the generation and optimization of operators; and these operators ultimately run steadily on domestic chips.

As Li Yuxuan, Chief Scientist of Intelligent Evolution at ModelBest, said, because code can be quickly verified by machines, engineering implementation will close the loop before theoretical research:

In the past, top operators like the FlashAttention series that require deep architectural reconstruction often took human experts months or even half a year to complete one iteration; now, within the team, the operator optimization tasks in which AI surpasses the best human implementation can be completed in at most two days.

And with the official open-sourcing of ForgeKernel, this method will also serve as infrastructure, providing a new efficiency path for domestic chip manufacturers and model teams.

Previously, for domestic chips to catch up with Nvidia, the difficulty was often not hardware metrics, but rather the expert experience and software layering accumulated over more than a decade in the CUDA ecosystem. But under the RSI paradigm, AI is completely breaking through this ecosystem barrier built by human labor over years, directly generating optimal solutions end to end.

As "domestic models write operators, domestic chips run operators" becomes the new operator engineering paradigm, the main body of R&D may be irreversibly shifting from humans to models. But this does not mean human experts are leaving the stage—only that the focus of their work has undergone a fundamental leap: