US sanctions 5 Chinese companies and plans to ban DeepSeek; Ministry of Commerce adjusts drone export controls

1. US sanctions 5 Chinese companies, including AI firms and venture capital institutions;

2. From "can run" to "dare to use": DAMO Academy wants RISC-V to ford the deep waters of mass production;

3. US plans to ban DeepSeek from participating in federal agency projects and contract signing;

4. Ministry of Commerce responds to optimizing and adjusting drone export control measures;

5. Intel's "Golden Hammer": exclusive mass production of 12-inch indium phosphide, pressing the accelerator on the silicon photonics era;

6. Mature-process market conditions are hot, with both prices and volumes rising; operations at VIS, Powerchip, and others get a boost

1. US sanctions 5 Chinese companies, including AI firms and venture capital institutions

On October 19 local time, the US State Department imposed sanctions on 5 Chinese entities under the Protecting American Intellectual Property Act (PAIPA), on the grounds that these entities stole trade secrets from US citizens. On the same day, the US Treasury Department's Office of Foreign Assets Control (OFAC) added the above companies to the Non-SDN Menu-Based Sanctions List (NS-MBS List), imposing asset freezes, financing restrictions, financial transaction restrictions, and investment bans, and simultaneously issued two general licenses providing limited authorization for specific transactions.

The list shows that the 5 Chinese companies sanctioned this time are: Shanghai Zhisuan Technology Co Ltd (Zhisuan) Shanghai Zhisuan Technology Co., Ltd., Qiji Chuangtan Beijing Investment Management Co Ltd (MiraclePlus) Qiji Chuangtan (Beijing) Investment Management Co., Ltd., Beijing Qiji Chuangtan Phase I Venture Capital Center Limited Partnership (Phase I) Beijing Qiji Chuangtan Phase I Venture Capital Center (Limited Partnership), Beijing Qiji Chuangtan Phase II Venture Capital Center Limited Partnership (Phase II) (Beijing Qiji Chuangtan Phase II Venture Capital Center (Limited Partnership)), and Beijing Qiji Chuangtan Zhiyuan Enterprise Management Center Limited Partnership (Zhiyuan Enterprise) Beijing Qiji Chuangtan Zhiyuan Enterprise Management Center (Limited Partnership). The Chinese names of the above companies are all consistent with the sanctions list published by OFAC.

The United States claims that Shanghai Zhisuan Technology was founded by Ding Linwei in 2023 and is mainly engaged in the development of AI-related technologies. Ding Linwei once applied in the name of this company to join the MiraclePlus startup incubation program, and during the project application and presentation process emphasized his knowledge of Google's internal AI technology and infrastructure, claiming to be able to replicate part of the technology of Google's supercomputing infrastructure and develop a software platform for accelerating machine learning tasks. The US State Department therefore determined that Shanghai Zhisuan Technology is suspected of participating in or benefiting from significant trade secret theft.

2. From "can run" to "dare to use": DAMO Academy wants RISC-V to ford the deep waters of mass production

On the morning of October 19, in Shenzhen, at the opening ceremony of the RISC-V China Summit. Meng Jianyi, Chief Scientist of DAMO Academy, gave a keynote sharing on the theme "From Stable and Reliable to Innovative Excellence—The Path of Technological Innovation and Open Ecosystem for XuanTie IP." This is a thought-provoking title: eight months ago, XuanTie C950 set a new global RISC-V performance record with a 3.2GHz main frequency and a SPECint2006 score exceeding 70, and the industry was still discussing "whether it can be fast"; today, Meng Jianyi no longer talked about those impressive data, but about multi-core, AI workloads, automotive-grade requirements, and one patch after another in the open-source community.

"Availability and mass production are two completely different stages." Meng Jianyi told Jiwei.com that availability means it can be demonstrated, while mass production means customers dare to put the chip into their own products. And after performance crosses the threshold, RISC-V has to answer a harder question: who will use it at scale?

Setting new records, changing the exam questions, C950 "gathering sand into a tower"

According to Omdia forecasts, RISC-V processor shipments will grow by about 50% annually, and by 2030 one in every four processors worldwide may be RISC-V. The "2026 High-Performance Milestones" list at the summit is also getting longer: Nvidia GB10 uses RISC-V cores as management controllers, and mainstream distributions such as Ubuntu continue to step up. High-performance RISC-V is turning from a declaration into a "schedule."

Performance is only one aspect; what is harder for RISC-V lies elsewhere. The XuanTie team has done the math: for a processor from project initiation to delivery, core R&D accounts for only 20%, and the remaining 80% is outside the core: whether the operating system can run, whether system manufacturers are willing to use it, and whom customers turn to when problems arise. The industry has never lacked samples; what it lacks is turning samples into something that can be mass-produced, delivered, and safely used by customers. In between lie a whole set of engineering issues—reliability verification, consistency assurance, toolchain maturity, and long-term maintenance capability—none of which can be solved by raising the benchmark score another five points. The industry saying "finally appearing after endless calls" describes the current situation: there are still not enough RISC-V application processors that can match mainstream solutions and still have a price advantage.

Looking at a longer timeline makes this clearer. In 2019, the C910 became the first to break the 2GHz clock speed barrier, proving for the first time that RISC-V has no inherent performance ceiling; the 2022 Wujian 600 platform and Yeying 1520 marked XuanTie's first systematic effort to address matters "beyond the core"—and it was this chip that enabled RISC-V to support Android for the first time and to run stably on laptops for the first time. Six billion units shipped over eight years were accumulated step by step along this path, not produced by a single launch event.

This is also why, after C950 set a new record, DAMO Academy turned around to make up the "eighty percent" of the homework. C950's position needs to be clarified: with a 3.2GHz clock speed and single-core SPECint2006 exceeding 70 points, it is the first time RISC-V has reached the same level as mainstream server CPUs; the previous generation C930, with 15 points/GHz of general-purpose compute, crossed the server threshold for the first time. Over the past six months, C950 has been continuously optimized:

First, moving from single-core high performance to multi-core high performance. The difficulty of multi-core lies in interconnect and coherence. Meng Jianyi offered an analogy: if a single core scores 100, then 100 cores should theoretically reach 10,000, but in practice only 7,000 is achieved—a linearity of 70%. The self-developed interconnect product XT-LINK pushes linearity to 78% at 128 cores, with total performance at 128 cores reaching 99.8 times.

Second, optimizing for Agentic workloads. After integrating general-purpose computing, matrix acceleration, memory bandwidth, and software collaboration, C950 leads mainstream architectures by an average of about 1.11 times across four types of Agentic workloads, with comprehensive AI performance improved by more than 10%; it reaches 43 tokens/second running Qwen3.8-Flash-Next and 38 tokens/second on DeepSeek V4-Flash.

One point to note here: RISC-V's advantage in inference lies not in stacking clusters, but in "unified general-purpose and inference computing." Agentic tasks first run a segment of general-purpose workloads, then hand off to AI, then return for processing—putting both into the same processor lowers latency, improves cost efficiency, and enables local deployment; cluster computing for ultra-large models remains GPU territory. Models under 30B collaborating with Agents are precisely where "general-purpose core + AI extension" products like C950 fit most clearly.

Servers and Agentic AI are the main battlefield, while automotive-grade and embodied intelligence are new fronts. The E908A released at the summit is the first RISC-V CPU to simultaneously achieve ASIL-B and ASIL-D, with its single-point fault metric (SPFM) exceeding 90% for the first time in the industry, and performance leading contemporary comparable competitors by about 20%, targeting safety islands, domain controllers, and automotive gateways.

Meng Jianyi said the automotive-grade threshold has never been just a core. It involves a complete software and hardware R&D and verification system; products must pass process certification and maintain consistency across more than a dozen vehicle models over a lifecycle of more than a decade. ASIL-D addresses reliability through hardware redundancy at high cost; ASIL-B addresses it through software means at low cost, but reliability must likewise be proven. Satisfying both simultaneously allows customers to trade off between safety level and bill-of-materials cost—this is the real meaning of E908A's "broad applicability."

XuanTie is not the industry's first to enter automotive-grade, and Meng Jianyi is candid: "We hope to bring two increments—first, to make reliability metrics higher than others, and second, to push automotive-grade product performance to unprecedented heights." In other words, what automotive-grade sells has never been a core, but traceable, reproducible determinism.

XuanTie also unveiled its automotive-grade processor roadmap: C925A and C930A moving up tier by tier, with the next-generation C950A targeting 5 times the performance of existing RISC-V automotive-grade products, planned for launch by the end of next year, aimed directly at autonomous-driving main controllers, with performance on par with C950 and adapted for automotive-grade use. "We want the RISC-V field to have products like NVIDIA's."

Why bet on Physical AI? Meng Jianyi's judgment is that Physical AI demands higher compute and real-time performance; today's general-purpose architectures are insufficient and must be extended, and RISC-V's customizability leaves exactly the room needed. Real-time control of a robot's "cerebellum" has been proven feasible, while high-performance computing for the "cerebrum" has greater headroom—and the latter precisely requires both compute and reliability, making it the harder and more valuable stretch. XuanTie targets autonomous driving because it is the most compute-hungry, and compute happens to be RISC-V's strength.

The ecosystem is a hidden thread, and even more a main thread

The talk also listed an open-source inventory: DAMO Academy ranks second globally in RISC-V contributions to the GCC community, bringing typical performance improvements of more than 10% to processors; more than half of OpenJDK's RISC-V code comes from DAMO Academy, and C950 achieves deep adaptation between RISC-V and server-side Java for the first time, with a 30% performance improvement; the RVI CSC certification baseline builds 2,796 open-source test cases; and as the only Chinese company among RISE founding members, it drives endpoint adaptation and donates development boards.

Commercial software is a tougher hurdle: most of what runs on RISC-V devices today is open-source software, and DAMO Academy is pushing for large applications such as Taobao, DingTalk, WeChat, and WPS to become gradually compatible.

Looking ahead, SMT in cooperation with the Beijing Institute of Open Source Chip and ZTE Microelectronics has achieved nearly 30% dual-thread gains; together they have advanced the AME instruction set extension to v0.6; and course co-building and platform co-creation with 10 universities are progressing in parallel. Talent is another hurdle: composite engineers who understand both instruction sets and engineering implementation have long been in short supply across the industry, and this is the real purpose of such cooperation.

This list also means that the role of Chinese companies is changing. In past instruction set competition, Chinese companies were basically rule takers; the rules for RISC-V are still being formed, and whoever contributes substantively has a say. AME means that Chinese teams are leading the effort to write the technical requirements of real-world scenarios into international standards.

However, the risk of phased fragmentation in RISC-V is real—once the choice space for ISA combinations, software platforms, and delivery chains gets out of control, the cost will ultimately be pushed onto software and customers. An ecosystem is not something one company writes into existence with code; it is the entire industry converging chaos into order. The gap is also real: OpenEuler has more than 30,000 x86 and Arm software packages, while RISC-V has fewer than 3,000. At present, the RISC-V industry is not only using binary translation to get existing software running first, but also actively using AI to lower migration costs.

Final thoughts

On the other side of the venue, the DAMO Academy booth is the "physical version" of this speech: cumulative shipments of more than 6 billion units, more than 200 mass-produced chips, and more than 400 customers form the booth's most eye-catching backdrop. The flow of the booth also mirrors DAMO Academy's logic: chips, platform, and ecosystem are arranged in three sections, precisely corresponding to "20% core, 80% beyond the core." The C950's large-model inference demo, the E908A automotive-grade solution, and the development boards and complete machines extended from Yeying 1520—after the speech ended, the aisle at the DAMO Academy booth was packed with attending guests. The industry's curiosity has shifted from "can it work" to "how will it be deployed."

Back to the original question: how far is RISC-V from the mainstream computing market? Meng Jianyi's answer is "three years." He believes two variables are at work simultaneously:

First, the window on the demand side. Applications in the Agent era have no interface, only workloads and API calls, and their dependence on the traditional desktop ecosystem has dropped sharply; combined with tight x86 and Arm supply, the east wind is indeed blowing. But he deliberately added: the supply chain is only the east wind; the core is that the application form has changed, and the opportunity belongs to teams that have products ready.

Second, patience on the supply side. It is normal for a high-performance CPU to take three years from project initiation to mass production, and another two to three years from mass production to scale ramp-up, with no revenue during the investment in between. Nvidia invested in CUDA for many years before the AI era arrived, and RISC-V's road will only be longer. In Meng Jianyi's view, the March launch was merely obtaining a "ticket to the 150-kilogram class competition," and after that the matches must be won one by one. Customers do not pay for sentiment; they only recognize whether the database can be handled and whether someone will take responsibility when problems arise.

This is also his deepest realization from more than 20 years of working on CPUs: delivery matters more than statements, and products are more substantial than metrics. The value of a processor does not depend on how powerful it is in itself, but on how many people have built things on top of it.

XuanTie is no longer satisfied with being a performance benchmark; it wants to deliver a "mass-production answer," using 6 billion shipments to prove that the road works, and using XT-LINK, E908A, Dragonwell, and 2,796 test cases to change "usable" inch by inch into "dare to use." A processor is never a success just because it has been built; it only counts once it is used.

3. The United States plans to ban DeepSeek from participating in federal agency projects and contract signing

The Trump administration has banned U.S. civilian government agencies from using products or services from Chinese AI startup DeepSeek, whose more affordable open-source models pose a growing challenge to Silicon Valley developers.

According to a notice published by the U.S. Department of Homeland Security on the Federal Register website on October 19, federal agencies must remove all DeepSeek products from their systems. The order cites U.S. cybersecurity law and bars the Chinese company from participating in federal government contracts.

The order sets out two hard requirements that take effect immediately: first, fully exclude information technology products and services from DeepSeek and its affiliated entities as defined by regulations from the procurement process, and remove relevant projects from all procurement channels, including agency-approved product lists, service provider directories, and government procurement e-commerce platforms. Second, civilian agencies are required to remove DeepSeek and its affiliates' products from IT systems, while also covering all third-party products and services developed based on DeepSeek technology.

Since DeepSeek's breakthrough R1 model shocked the global market early last year, the company has been closely watched by Washington policymakers, who believe it may pose a potential threat to U.S. national security.

4. The Ministry of Commerce responds to the optimization and adjustment of drone export control measures

On October 19, the spokesperson of the Ministry of Commerce answered reporters' questions on the optimization and adjustment of export control measures for drone-related items.

A reporter asked: On October 19, 2026, the Ministry of Commerce, together with relevant departments, jointly issued an announcement to optimize and adjust export control measures for drone-related items. What are the considerations?

The Ministry of Commerce stated:

In accordance with the Export Control Law of the People's Republic of China and other relevant laws and regulations, on October 19, the Ministry of Commerce, together with relevant departments, issued an announcement on optimizing and adjusting export control measures for drone-related items. The relevant measures will officially take effect on November 18. Previously, we had notified relevant countries and regions that have established export control dialogue mechanisms with China.

The drone-related items involved in these measures have obvious dual-use characteristics. China has optimized and adjusted the relevant measures in accordance with laws and regulations, with the aim of safeguarding national security and interests and fulfilling international obligations such as non-proliferation. At the same time, China is committed to maintaining the security and stability of global industrial and supply chains, and will review relevant export license applications in accordance with laws and regulations; applications that meet the requirements will be approved.

Dynamically adjusting export control measures is a common international practice. In recent years, the global drone industry and technology have developed rapidly, and some products that were previously advanced are now mass consumer products. In the process of implementing export control measures, China has actively listened to opinions and suggestions from all parties and, after careful assessment, promptly optimized and adjusted the relevant measures. This optimization and adjustment of drone export control measures is based on the latest industry and technological developments reported by the industry. It fully reflects China's firm opposition to the illegal use of drones for non-peaceful purposes, while firmly supporting Chinese enterprises in conducting international trade and cooperation in drones for civilian use.

China is willing to use bilateral export control dialogue and exchange mechanisms to conduct communication and dialogue with relevant parties on export control policies and practices, while listening to opinions and suggestions from all parties, further earnestly fulfilling international obligations such as non-proliferation, and actively promoting and facilitating compliant trade.

5. Intel's "Golden Hammer": Exclusive mass production of 12-inch indium phosphide, pressing the accelerator on the silicon photonics era;

Intel announced exclusive mass production of 300mm indium phosphide silicon photonic wafers, with cumulative shipments of more than 8 million optical transceivers and 32 million integrated lasers, and a target energy consumption of less than 5 picojoules per bit for its photonic systems. Driven by AI clusters, optical components are in short supply, and the data center optical interconnect market is expected to reach $144.4 billion by 2030. Nvidia, Broadcom, and TSMC are racing toward CPO, and the industry has entered its first year of mass production.

At the recently held 2026 Open Compute Project (OCP) Global Summit, Intel unveiled its silicon photonics vision and 300mm (12-inch) silicon photonic wafer technology. Nick Dube, Vice President of Intel's Data Center Systems and Solutions, called silicon photonics the "golden hammer" for next-generation systems and claimed that Intel is the only high-volume foundry capable of supplying 300mm indium phosphide (InP) silicon photonics technology to the entire industry at scale, for near-packaged optics (NPO) and co-packaged optics (CPO) in AI/HPC.

Why silicon photonics? Dube's judgment is that the chip industry is simultaneously hitting ceilings in three dimensions: transmission distance, bandwidth density, and energy per bit, and silicon photonics can solve these constraints all at once. For rapidly expanding AI clusters, the efficiency of data movement among massive numbers of GPUs, CPUs, and memory pools has directly constrained overall system performance gains.

The bottleneck is not abstract; it is already visible on the supply side. The market is focused on GPUs, but the shortage lies in a beam of light: as AI clusters scale up, optical module speeds are rapidly iterating from 400G/800G to 1.6T and 3.2T. TrendForce estimates that global optical module shipments in 2026 will be about 70 million units, of which more than 52 million will be 800G and above; LightCounting notes that demand exceeds supply by about 30%, Nvidia has strategically locked up capacity from major EML chip suppliers, and lead times in the spot market extend beyond 2027; Jefferies estimates a shortage of about 10% for 800G optical modules and 30% for 1.6T, while the combined 2026 capital expenditure guidance of the four major overseas cloud providers is about $710 billion. Optical communications have become a new bottleneck for AI, and laser chips and indium phosphide materials have long been in short supply.

From 150mm to 300mm: the "size revolution" of indium phosphide

To understand Intel's move, one must first understand the industrial position of indium phosphide. Silicon is an indirect bandgap material and cannot efficiently emit light by itself; indium phosphide has a direct bandgap and is the core material for laser chips—the industry summarizes this as "silicon handles light guiding, InP handles light emission," and the two are complementary rather than substitutes.

The problem lies in size. The industry's conventional indium phosphide substrates remain at the 150mm (6-inch) level, with mainstream sizes even mainly 3 to 4 inches, a significant gap from the 300mm standard of silicon-based CMOS; InP crystals are brittle, grow slowly, and are difficult to control for defects, and the number of laser chips that can be cut from each wafer is far lower than from large-size silicon wafers, so capacity expansion is noticeably slower than in the mature silicon wafer industry. Intel's solution is to integrate indium phosphide light source technology into the 300mm silicon wafer process, thereby raising manufacturing efficiency and capacity scale—according to the plan, these 300mm wafers will carry the cutting-edge materials needed for future NPO and CPO functions in HPC and AI.

Reliability is another pillar: since commercialization in 2016, Intel has cumulatively shipped more than 8 million optical transceivers and 32 million integrated lasers, and its hybrid lasers have a failure rate of less than 0.1 FIT in accelerated life testing, validated based on three years of data from more than 6 million field-deployed lasers. For systems requiring "maintenance-free" integrated light sources, this constitutes a substantial barrier to entry. Intel also said it will promote community standards for external light sources and provide multi-wavelength light sources manufactured at its U.S. fabs.

Energy consumption is the most emblematic metric: Intel expects photonics systems to reduce energy consumption to below 5 picojoules per bit—described as a long-awaited industry threshold; in disclosures at the 2026 Optical Fiber Communication Conference (OFC), its optical compute interconnect chiplet for AI scale-up scenarios likewise sets an end-to-end power efficiency target of below 5 pJ/bit, with a bandwidth density target exceeding 1 Tb/s/mm. Notably, as early as 2022, Intel Labs demonstrated an 8-wavelength distributed feedback laser array fabricated on a 300 mm hybrid silicon photonics platform, emphasizing at the time that scalable production could be achieved using existing fab processes—today's "golden hammer" is essentially pushing the manufacturing roadmap from four years ago to the forefront of industrialization.

Industry race: NVIDIA in mass production, Broadcom iterating, TSMC positioning

Intel's narrative is not an isolated case; the industrialization of silicon photonics and CPO is advancing simultaneously on multiple fronts.

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Broadcom's rhythm is platform iteration: in 2025 it launched its third-generation CPO platform, achieving a 200G transmission rate per channel, and is simultaneously developing a fourth-generation 400G/lane solution; by building automated testing and mass production mechanisms with partners such as Corning and Delta Electronics, the company officially says CPO can save more than 30% of overall system power consumption; its 51.2T Bailly CPO switch has also begun small-batch shipments, with hyperscalers such as Meta completing deployment validation. TSMC, meanwhile, has chosen to position itself in manufacturing: its Compact Universal Photonic Engine (COUPE) integrates high-speed micro-ring modulators, Ge detectors, and electronic chips at advanced nodes such as 3 nm on a 300 mm SOI and 65 nm photonics platform, then integrates them all the way through SoIC, hybrid bonding, and CoWoS; in May 2026, the world's first 200Gbps micro-ring modulator using COUPE technology was announced to have entered mass production. ASE and its subsidiary Siliconware have also invested in R&D of silicon photonics and CPO packaging technologies. The capital level is equally hot: over the past year, the global AI industry has invested more than $15 billion in co-packaged optics, photonic chips, high-speed transceiver modules, and optical fibers; Marvell acquired photonic interconnect startup Celestial AI for $3.25 billion, Ayar Labs completed a $500 million fundraising round, and SpaceX has also obtained regulatory approval to acquire optical transceiver manufacturer Mesh.

Chart interpretation: the optical interconnect market is expected to grow from $13.7 billion in 2024 to $144.4 billion in 2030, more than a 10-fold increase in six years, with silicon photonics expected to account for 63.7% of AI data center optical interconnect revenue.

China's strength: optical module leaders transforming and optical chips catching up

Domestically, the CPO industry chain presents a pyramid pattern of "overseas leading, domestic accelerating to catch up and replace": overseas, Broadcom and NVIDIA are the core and dominate industry standards; in the domestic market, Zhongji Innolight, Eoptolink, and TFC Optical Communication form the first tier, with outstanding competitiveness in 1.6T CPO modules and optical engines, while Accelink Technologies and HGTECH focus on high-end chip R&D and technological breakthroughs.

Leading manufacturers are taking the most concrete actions. Zhongji Innolight, as the global optical module leader, has taken the lead in building a dedicated CPO production line; its 800G CPO optical modules have achieved small-batch mass production and are deeply tied to leading AI computing manufacturers such as NVIDIA and Google; the company is also transforming into a subsystem-level solution provider through in-house development and production of silicon photonic chips and a full-path layout of NPO/XPO/OCS/CPO—some customers have already given clear NPO demand guidance and orders, with shipments expected in 2027, and more customers are expected to launch NPO solutions in 2028. Eoptolink has built a technology system covering multiple interconnect forms such as pluggable optical modules, LPO/LRO, XPO, NPO, and CPO, and expects demand for NPO order delivery to emerge in the second half of 2027, with shipment volumes gradually increasing in 2028. Cambridge Technology also launched customized development of 12.8T XPO and multiple NPO products in the first half of this year.

Cloud vendors are following suit as well: in September this year, Huawei released Ascend 960, the world's first super node adopting NPO technology, targeting training and inference for large models with a scale of ten trillion parameters; subsequently, Alibaba Cloud released the Panjiu AL64 distributed SNPO optical interconnect super node, becoming the world's first super node server to implement SNPO; Tencent Cloud also stated that it will deploy NPO super nodes starting from the fourth quarter of 2026. Leading domestic cloud vendors believe that NPO is one of the optical interconnect solutions currently most suitable for deployment in China. There have also been breakthroughs in the upstream segment: in the optical chip field, Yuanjie Semiconductor, Everbright Photonics, and Accelink Technologies are core domestic laser targets; Wogo Photoelectric's TGV glass substrate for 1.6T CPO optical modules has completed sample delivery and testing with leading companies such as Zhongji Innolight; Sanan Optoelectronics has achieved supply of chip samples at an energy consumption level of 1-2pJ/bit, adapting to the requirements of 800G and 1.6T CPO solutions; the midstream optical engine and packaging are the core incremental value of CPO. Tianfu Communication, as a core supplier of optical engines, directly benefits from CPO mass-production orders, and Universal Scientific Industrial's optical engine capacity is planned to increase to 200,000 units per month by the end of the year.

However, the gap is equally clear: domestic enterprises currently mainly participate in mid- and back-end segments such as device assembly and complete-machine integration, while high-end laser chips, core silicon photonics processes, and core advanced packaging technologies are still dominated by enterprises from other regions, and industry profits are accelerating toward high-barrier upstream segments such as optical chips, optical engines, and advanced packaging. Industry analysis believes that the localization rate of the entire domestic CPO industry chain is expected to exceed 80% around 2029, on the premise that the three major bottlenecks of silicon photonic chips, InP lasers, and advanced packaging are overcome simultaneously. In terms of the time window, large-scale commercialization of CPO is expected to unfold in 2027 to 2028, leaving Chinese manufacturers about a two-year catch-up period—pluggable optical modules will still be the core of cloud vendors' networks in 2026 to 2027, and "using traditional business to nurture new technology" has become a feasible transformation strategy. Policy and expectations are also providing support: the National Development and Reform Commission disclosed that during the "15th Five-Year Plan" period, the construction of computing power networks will add 4 trillion yuan in direct investment, and the Ministry of Industry and Information Technology regards optoelectronic chips, CPO devices, and others as the foundation for AI development; Goldman Sachs predicts that CPO penetration will be only 29% in 2028, and 1.6T pluggable orders have been scheduled through 2028. The industry consensus is that CPO is not a replacement for pluggables, but rather opens up a new incremental market.

Chart interpretation: According to QYResearch statistics, global CPO market sales were US$768 million in 2025, are expected to reach US$1.061 billion in 2026, and will reach US$9.051 billion in 2032, with a compound annual growth rate of 42.9%—from "speculating on expectations" to "watching for volume ramp-up," the inflection point has appeared.

Future outlook: trust, standards, and 5 picojoules

Back to Intel: when a company simultaneously plays the triple roles of chip designer, system architecture promoter, and foundry, how much trust its commitment to "serving the entire industry" can win remains to be seen; Dube acknowledged that the team is working "day and night" to advance silicon photonics into implementation in the coming years. The direction is certain: 2026 is widely recognized by the industry as the first year of CPO mass production, and the value center of optical interconnect is shifting from pluggable optical modules to upstream optical engines, laser light sources, and advanced packaging. For Intel, exclusive mass-production capability, a reliability record, and external light source standards form a combined punch; the endgame of this "war of light" is who first turns 5 picojoules per bit into reality in the data center.

6. Mature-process market conditions are hot, with both prices and volumes rising; operators such as VIS and Powerchip benefit

The latest report from research institute Sigmaintell points out that the expansion of AI infrastructure has driven up demand for power management, communications, and peripheral chips. This quarter, global mature-process wafer foundry industry capacity utilization has climbed to a high level of 91%. Along with higher material costs and tight supply and demand, mature-process 8-inch and 12-inch wafer foundry prices will rise by 4% to 8% quarter-on-quarter in the first quarter of next year.

UMC is positive on the market outlook, optimistic that demand for 22nm and 28nm will continue to recover, with third-quarter wafer shipments expected to increase by a high single-digit percentage quarter-on-quarter, capacity utilization climbing above 90%, average selling prices stable, and gross margin at about 35%.

As for VIS, benefiting from warming AI power management demand, third-quarter capacity utilization reached above 90%, order visibility is about four months, and there is still room for further improvement in the fourth quarter.

VIS estimates that its third-quarter gross margin will range from 32.5% to 34.5%, and that with subsequent improvements in volume, price, and product mix, operating momentum is expected to continue, while its new 12-inch fab in Singapore supports medium- and long-term growth demand.

As for Powerchip, in July this year it raised DRAM wafer input prices by about 45%, and simultaneously raised 8-inch and 12-inch logic foundry wafer input prices by 10% to 15%, with the effects of the price adjustments continuing to be reflected in the second half of the year. The company focuses on memory, logic foundry, and 3D AI Foundry, and is deploying wafer stacking, silicon capacitors, and silicon interposers; the company emphasized that after selling the Tongluo P5 plant to Micron, it will help reduce liabilities and ease pressure from depreciation and fixed costs, advancing operational improvement.

Sigmaintell points out that global mature-process demand is diverging: buying sentiment for consumer electronics such as smartphones and notebooks remains relatively weak, but the expansion of AI infrastructure has pushed up demand for NOR Flash, high-performance microcontrollers (MCUs), and power management chips, driving tight capacity for 55nm and 90nm. Among them, 90nm quotes have already risen 4% quarter-on-quarter this quarter, and are estimated to rise another 8% in the first quarter of next year, the most prominent increase.

As for 28nm and 40nm, although prices this quarter are flat, benefiting from the gradual recovery in demand for communications, display driver ICs, and image signal processors, plus the pass-through of cost pressure, quotes are estimated to rise by 6% and 5% respectively in the first quarter of next year; although some second-tier wafer foundries are using low prices to compete for 55nm and 90nm orders, their product mix is differentiated from that of mainstream players, so the impact on overall prices is limited.

Sigmaintell judges that supply and demand in the 8-inch mature-process wafer foundry market will become even tighter. Demand for 48V high-voltage power management chips required by AI servers is expanding, and industry players generally have order visibility of about half a year. Moreover, global 8-inch wafer foundry capacity will shrink by 6% and 2% this year and next year respectively, while capacity expansion takes time. Quotes in the first quarter of next year are expected to rise by about 4%, and the upward trend is expected to continue into next year. (Source: Economic Daily)