XHEART New Core Voyage Releases X7 Ultra Automotive-Grade Chip, 700TOPS Compute Already in Mass Production with Over 200,000 Units Shipped

A domestic chip company founded three years ago has had its first chip in mass production for 8 months, with cumulative shipments exceeding 200,000 units.

Xin Dongxi, October 30 news: Recently, XHEART XINXIN HANGTU officially debuted in Suzhou and released its flagship product, the X7 Ultra, which boasts 700TOPS of large-model computing power.

Rather than simply increasing chip computing power, XHEART chose the forward-looking technical route of "large models defining chips," that is, designing the chip architecture according to the computational requirements of large models so that the chip can run large models more efficiently.

▲Overview of X7 Ultra core parameters

According to data disclosed by XHEART, in real-world mass-production intelligent-driving model tests, the X7 Ultra achieved a chip computing utilization rate of 98.7%; under conditions of comparable large-model performance, memory bandwidth consumption dropped by 80% compared with industry flagship products.

By optimizing the computing architecture and data movement efficiency, the X7 Ultra also achieved a 10x release of model parameters.

Behind these figures is an important change facing intelligent-driving chips and even large-model chips.

As end-to-end large models accelerate their deployment in vehicles, chips must not only provide higher computing power but also solve the problems of data movement, storage bandwidth, and power consumption during model operation.

XHEART hopes to improve the chip's actual computing efficiency through an innovative super-core NPU architecture and native software-hardware co-design.

1. As intelligent-driving large models enter vehicles, chips cannot rely solely on stacking computing power

End-to-end large models are changing the way intelligent driving systems compute.

In the past, intelligent driving mainly relied on different modules such as perception, prediction, and planning to handle tasks separately, with each module running its corresponding algorithm model.

Today, end-to-end large models integrate more tasks into large neural networks. As model scale and computational complexity continue to rise, the requirements for vehicle-side chips are changing accordingly.

Chip computing power is getting higher and higher, but models may not be able to fully utilize that computing power.

After a large model completes a computation, it may need to write the results to external memory, and subsequent operations then read them back out.

If data frequently travels back and forth between computing units and memory, even if the chip has very high computing power, a large amount of time will be consumed on data transmission.

This is what is often called the "memory wall" problem in chip design.

At the same time, data movement also consumes power. For vehicles with limited space, power, and heat dissipation conditions, data access efficiency directly affects the performance and cost of the entire intelligent-driving computing platform.

Therefore, in addition to increasing TOPS, chipmakers also need to consider how to enable computing units to obtain data faster, reduce memory access, and lower operating power consumption.

Another problem is that the chip development cycle is far longer than the algorithm iteration cycle.

It usually takes several years for a chip to go from design to mass production, and algorithms may have already been updated through multiple versions during that time.

If a chip is designed only for the current model, it may face new algorithm requirements by the time the product reaches mass production.

▲Large models defining chips

When XHEART initiated the project in 2023, it chose a different approach: first study what computing and storage capabilities large models require, and then design the chip architecture accordingly.

Under this approach, the algorithm team participates in advance in the chip's technical definition, studying the computational characteristics, data access methods, and key operator requirements of future models.

The chip team then uses this information to determine the design plans for the NPU architecture, storage hierarchy, data paths, and software toolchain.

XHEART calls this "large models defining chips."

The core of this route is to move algorithm-hardware co-optimization earlier into the chip design stage, so that the chip architecture is built around the operating requirements of large models from the very beginning.

2. The super-core NPU arrives: how does the X7 Ultra improve effective computing power?

The super-core NPU adopted by the X7 Ultra is the key to realizing the technical idea of "large models defining chips."

For large Transformer models, if multiple small computing cores are used to run them jointly, the model may need to be split into different parts, with computing tasks distributed among multiple cores.

Although this can utilize multiple computing cores, different cores need to exchange data, and it may also involve additional task scheduling and intermediate result storage.

XHEART chose to concentrate more computing tasks inside a super core, trying to keep the complete end-to-end large model running within one large core and reducing cross-core data exchange.

According to the technical plan published by XHEART, the X7 Ultra integrates the hundreds-of-GB/s-level data interaction between traditional small cores into TB/s-level high-speed interconnect inside the super core, allowing data to flow faster within the chip.

▲Super-core NPU design

However, making the computing core larger is only the first step; reducing unnecessary data movement is equally important.

When large models run, they frequently perform operations such as Layer Norm, Transpose, and Summation.

These operations themselves may not necessarily require particularly high computing power, but if data must be read from external memory and the results written back every time, a large amount of storage bandwidth will be consumed.

To this end, XHEART optimized the on-chip data processing path for these high-frequency operators and configured dedicated acceleration units.

Some computations can be completed directly inside the chip, or even without leaving the registers, thereby reducing access to external DDR memory.

This has two benefits: first, it shortens data transmission time and reduces waiting by computing units; second, it lowers the power consumption caused by data reads and writes, easing the heat dissipation pressure on the entire computing platform.

In addition to data access, the X7 Ultra also optimizes the way computations are performed inside the NPU.

During large-model inference, the compute units must continuously load model weights. If the next step of computation can only proceed after all weights have finished loading, compute resources will sit idle.

Through software-hardware co-optimized task scheduling, the X7 Ultra allows computation and weight loading to proceed in parallel, enabling more compute units to work simultaneously.

According to the measured results of the mass-production intelligent driving large model published by XHEART, the X7 Ultra achieves a compute utilization rate of 98.7%.

▲X7 Ultra hardware efficiency

Beyond hardware, XHEART also redesigned its AI toolchain.

A large model cannot run directly on a chip; the toolchain is still needed to perform model conversion, quantization, compilation, and deployment.

If the toolchain cannot reasonably arrange compute tasks, then even if the hardware itself is powerful, problems such as compute units waiting and repeated data reads and writes may still occur.

The X7 Ultra adopts whole-network fusion technology to uniformly orchestrate the compute tasks of the entire model, processing mergeable operations together and reducing the repeated writing of intermediate results to external memory.

This design also helps adapt to continuously upgraded algorithm models. When models change in the future, the deployment of compute tasks can be adjusted through the toolchain without having to modify the chip hardware each time.

In terms of computational precision, XHEART sets a constraint that the similarity between the quantized model output and the FP32 floating-point model must reach 99.99% or above, so as to avoid performance optimization affecting model precision.

Based on the above architecture and toolchain optimizations, the X7 Ultra ultimately achieves 700TOPS of large-model compute power.

▲Large-model compute power reaches 700TOPS

Under comparable large-model performance, comparison results show that the X7 Ultra's memory bandwidth consumption is 80% lower than that of flagship industry products, while energy efficiency is improved by 100%.

Lower memory bandwidth consumption means that when running models of the same scale, the chip requires fewer external storage resources. The resources saved in this part also create conditions for deploying larger models.

According to XHEART, the X7 Ultra achieves a 10x release of model parameters.

In addition to the NPU, the X7 Ultra is also the first automotive-grade chip to adopt and launch in mass production an Armv9 automotive-grade CPU. It is responsible for complex control and system scheduling, and handles different types of tasks through dedicated compute units.

▲The chip adopts Armv9 automotive-grade IP

In terms of the LiDAR processing accelerator, the chip supports data processing capability with a processing bandwidth of up to 20 million points per second, and can complete the relevant preprocessing work within dedicated compute units, reducing occupation of other compute resources.

From the super-core NPU and dedicated operator acceleration to AI toolchain optimization, the X7 Ultra does not simply add compute units; rather, it simultaneously optimizes computation and data processing methods, enabling the 700TOPS of compute power to be more fully used for large-model inference.

However, having an excellent design is far from enough; engineering and mass-production capability are also indispensable.

III. From Architecture Simulation to 200,000 Units Shipped: Large-Model Chips Move Toward Mass Production

For a chip company, designing a chip is only the first step. Whether it can successfully tape out, complete automotive-grade validation, and achieve mass-production delivery is equally important.

For XHEART, it took about two years from its founding in 2023 to the mass production of the X7 series chips.

In the early stage of chip development, XHEART evaluated multiple architecture options.

XHEART CEO Li Zonglin has publicly stated that different chip architectures use different data flow designs, and the team needed to build performance models in advance, compare the computational efficiency of each option through simulation, and then decide the final architecture route.

After completing the architecture design, XHEART also cooperated with Momenta to conduct full-chip simulation verification using a real mass-production intelligent driving large model.

This step was completed before chip tape-out, allowing early checks of algorithm-hardware compatibility and reducing the risk of problems only being discovered after the chip comes back.

At the same time, XHEART also carried out domain controller design with automakers in advance, advancing the integration and verification of the chip with other components in parallel, rather than waiting until chip manufacturing was completed.

These early efforts significantly shortened the software-hardware integration time after the chip came back.

According to information disclosed by XHEART, after the first X7 series chip came back, it was powered on in less than 24 hours, with all main data paths connected.

On the 17th day after the chip came back, the X7 series chip, underlying software, and intelligent driving large model achieved a full-vehicle closed loop, and testing began on real roads in scenarios including daytime, nighttime, and heavy rain.

Subsequently, XHEART worked with automakers to advance mass-production projects, provided domain controller reference designs, and carried out domain-controller-level PreDV verification to help customers complete the integration of chips and full vehicle systems.

At present, the X7 series has achieved actual mass-production results.

▲X7 series mass-production report card

As of the press conference on October 29, the X7 series chips had been in mass production for 8 months, with cumulative shipments exceeding 200,000 units, installed in 10 mass-production vehicle models, and orders obtained for more than 40 vehicle models.

From chip bring-up and algorithm adaptation to full-vehicle mass production, XHEART has completed the commercial delivery of its first-generation product and begun to expand shipment scale through multiple vehicle model projects.

In terms of the cooperation ecosystem, Momenta is an important strategic partner of XHEART, and the two sides have carried out algorithm-hardware collaboration since the chip design stage.

However, XHEART is an independently operated chip company and does not have an exclusive binding relationship with Momenta.

Its chips are open to OEMs and all algorithm vendors, and other algorithm solution providers can also adapt and develop based on XHEART chips.

At this press conference, Momenta CEO Cao Xudong also introduced the latest progress of the two sides' joint development.

According to his disclosure, with the support of X7 Ultra, the parameter scale of the upcoming R7 Ultra model will be expanded by 5 to 10 times, and safety performance will be improved by more than 5 to 10 times.

▲User experience development timeline

This also reflects the practical application direction of joint algorithm-chip design: by optimizing the underlying computing platform, the vehicle side can run intelligent driving large models with more parameters and more complex computing tasks.

In addition to the current assisted driving market, XHEART has also begun to expand into L3 and L4 autonomous driving.

Compared with L2 assisted driving, higher-level autonomous driving places higher requirements on the reliability, functional safety and redundancy capabilities of the computing platform.

In terms of chip safety design, X7 Ultra meets the ISO 26262 ASIL-B functional safety requirements, and the integrated safety MCU has passed ASIL-D certification.

For L3 and L4 applications, XHEART has also launched a computing platform based on dual X7 chips, providing redundancy in computing and safety capabilities through the interconnection of two chips.

According to information announced at the press conference, the dual-X7 computing platform has already been nominated for multiple vehicle model projects.

Regarding next-generation products, XHEART announced the R&D goals for the X9 chip.

According to the plan, the X9's large-model computing power will reach 3000TOPS (only for physical AI scenarios such as intelligent driving), and single-chip memory bandwidth will reach 700GB/s, targeting scenarios such as L4 autonomous driving, next-generation world models and embodied intelligence.

▲X9's large-model computing power

As the scale of model parameters continues to expand, the vehicle side not only needs more computing resources, but also higher storage bandwidth and more stable and reliable system operation capabilities.

From the mass production of the X7 series chips, to X7 Ultra improving large-model operating efficiency, to X9 raising computing and storage specifications, XHEART is advancing product iteration along the route of "large models defining chips."

Conclusion: Large-model chips enter the stage of system efficiency competition

The X7 series chips achieving large-scale mass production shows that XHEART already has the delivery capability for automotive-grade large-model chips. X7 Ultra further focuses the competition on model operating efficiency.

As autonomous driving evolves toward L3 and L4, models will continue to raise requirements for computing, storage and functional safety. For chip manufacturers, the future requires not only improving computing power specifications, but also making the added computing power effective in real models.

From this perspective, software-hardware collaboration capability is becoming an important competitive factor for intelligent driving chips, and XHEART is providing the industry with a highly valuable reference model.