Dongfang Suanxin's 128-card 3D chip cluster goes live, sprinting toward thousand-card delivery by year-end

Register/Log in 3D high-compute chip cluster lands for the first time, domestic compute takes a new path Original source: Semiconductor Industry Observer Published: 2026-10-21 17:10 Author: Peng Cheng Compute chips manufacturing Generate poster Domestic compute has started competing on delivery efficiency.

In October in Shanghai, at the first-ever "National Chip Exhibition" set up at the Industrial Fair, three data cards on the Dongfang Suanxin booth were photographed by many: the world's first verified 3D chip cluster system, completing training adaptation for mainstream large models in 7 days, and running the full chip-software-cluster chain in 24 months.

Taken individually, each is a typical launch-event number. Taken together, the three numbers point to three capabilities: system-level verification capability, software adaptation speed, and industrialization delivery efficiency. The common landing point of these three capabilities is another thing the company announced at the National Chip Exhibition: a 128-card cluster system running stably, large-scale training cluster delivery already achieved, and thousand-card-level cluster delivery by the end of the year.

Looking across the industry, over the past two years domestic compute chips have been released densely, with single-card parameters constantly approaching overseas flagships, but between parameter announcements and scale delivery lies a long engineering cycle. Professor Wei Shaojun has deep insight that AI applications now update rapidly on a weekly basis, large-model algorithms iterate and upgrade on a monthly basis, but chip R&D iteration takes years as a cycle, and after system deployment it can run stably for 5 to 10 years. This severe imbalance in iteration rhythm places extremely high demands on chip design and system adaptation.

01 First, 7 days, 24 months: three sides of one delivery

Dongfang Suanxin emerged precisely with the goal of resolving this gap. The company was founded in May 2024 in Zhangjiang, Shanghai; at the end of April this year it completed A+ round financing, with a post-investment valuation of 12.275 billion yuan, and the National Artificial Intelligence Industry Fund among its shareholders; in September it completed joint-stock reform and plans to launch B round financing in the fourth quarter. Chairman Wei Shaojun is a tenured professor at Tsinghua University and vice chairman of the China Semiconductor Industry Association, and the team grew out of Tsinghua's nearly two decades of research accumulation in reconfigurable computing. In two and a half years since founding, Dongfang Suanxin has completed the full closed loop from chip R&D and full-stack software adaptation to large-scale deployment of hundred-card-level training clusters, and compressed the entire process into 24 months. How was this delivery pulled off? The answer is hidden in the three numbers.

First is the world's first verified 3D chip cluster system. Between lighting up a single card and scale deployment lies not only a difference in quantity, but a qualitative difference in engineering difficulty. Before this, 3D-stacked high-compute chips had remained at the paper and sample stage. As one of the key technologies of 3D stacking, hybrid bonding was used by Sony around 2016 for image sensors, and in 2018 Yangtze Memory used it for 3D NAND; for nearly a decade thereafter, the main application scenarios of this process remained sensors and flash memory. Applying the same process between DRAM and AI logic chips, and then forming clusters for continuous large-model training, had never been done before.

More critically, once high-compute chips form clusters, the problems are amplified. With hundreds of chips training collaboratively, any single chip's link stability, memory reliability, or temperature control issues will be exposed during long continuous operation. For training clusters, 72 hours is a recognized threshold. Only under sufficiently long continuous load can the system's weak links have nowhere to hide. According to disclosures by Dongfang Suanxin at the National Chip Exhibition, the 128-card DF1000 training cluster trained continuously for 72 hours without interruption, with training accuracy meeting standards, and has carried training tasks for multiple large models including Llama2-70B and Step 130B.

On the supply chain side, DF1000 completes the closed loop entirely within the domestic industrial chain, from chip design, 14nm wafer manufacturing, 3D hybrid bonding packaging to packaging and testing, while on the cluster side switches and network cards directly use mature domestic products. The most important value of DF1000 lies in achieving a fully domestic supply chain, rather than leading on individual performance metrics. Given the reality of uncertainty in advanced process and HBM supply, a fully domestic closed loop is itself a capability that needs verification. What was verified this time is not only the chip, but also the quality of the entire domestic supply chain in supporting large-scale training.

Second is completing training adaptation for mainstream large models in 7 days. Customers truly care about only one question: can their model run, and at what cost. The figure disclosed at the National Chip Exhibition is: the hundred-billion-parameter-level Step 130B large model completed training adaptation in only 7 days. In the past, teams migrating domestic compute often needed months of manpower investment for cross-platform adaptation, involving operator rewriting, precision alignment, communication tuning and regression testing, which was the biggest hidden cost for customers choosing domestic chips. Seven-day adaptation turns "migration" from a project into a process step.

Finally is running the full chip-software-cluster chain in 24 months. Under the industry's conventional rhythm, from chip tape-out and software adaptation to cluster setup often takes three to four years. Dongfang Suanxin's path is three lines in parallel: chip design, compiler and operator library development, and cluster system architecture advance simultaneously with collaborative verification, rather than waiting for tape-out success before starting software, or waiting for software adaptation to finish before building the cluster. From the company's founding in May 2024 to delivery of the first fully domestic large-scale training cluster, the whole process took 24 months.

Parallelism can hold only if each stage is sufficiently deterministic. After the DF1000 accelerator card came back from tape-out, all specification tests—compute, memory bandwidth, communication bandwidth, power and temperature—were completed in one pass, and all 11 BF16 operator tests passed on the first attempt. The effectiveness of hardware-software co-design on silicon reduced rework in subsequent stages. On the cluster side, a standardized delivery process of "deployment—joint debugging—stress testing—trial training—acceptance" has been established, making the entire process from infrastructure adaptation to large-model training capability controllable.

02 Where does efficiency come from: architecture, R&D, operations, supply chain

Part of this efficiency can be explained at the level of engineering organization, but the more fundamental answer lies in the choice of technology route. For practitioners concerned with domestic compute, judging a compute company's true level mainly comes down to three things: total cost of ownership (TCO), delivery capability, and software ecosystem. Dongfang Suanxin supports all three through its technology route of near-memory computing plus software-defined architecture.

In architecture, 3D-stacked near-memory computing breaks through the "memory wall" bottleneck. Traditional high-end AI chips use a separated architecture of "compute cores + external HBM," with bandwidth bottlenecks compensated by advanced processes and more complex packaging; data travels long distances between compute units and memory units, driving up power consumption and cost. DF1000's choice is to change the way memory and compute are connected at the root: DRAM wafers are bonded directly above logic wafers, with copper pads aligned for direct connection, no bumps and no interposer in between, compressing interconnect pitch from tens of microns to the sub-micron level and achieving per-chip memory access bandwidth of 6.4TB/s. This bandwidth level exceeds the official specifications of mainstream AI chips using HBM memory: H100 at 3.35TB/s, H200 at 4.8TB/s, and MI300X at 5.3TB/s. DF1000 achieves HBM3E-level bandwidth on a 14nm process without using HBM. The bandwidth advantage continues to grow in the roadmap: the DF2000, planned for launch in Q4 this year, will raise memory access bandwidth to 15TB/s, surpassing B200's 8TB/s.

In R&D model, a unified technology stack enables cross-generation reuse and lowers adaptation costs. In the traditional model, chips, basic software, and cluster systems often belong to different vendors; cross-architecture and cross-platform adaptation requires repeated investment, and every hardware upgrade means re-adapting the entire chain. Dongfang Suanxin's approach is to develop everything in-house, from chip architecture to compilers, operator libraries, collective communication libraries, distributed training frameworks, and cluster scheduling and operations tools. Information shows that Dongfang Suanxin has fully self-developed the full-stack CAAP software stack, covering compilers, operator libraries, distributed communication libraries, training frameworks, and one-stop development tools. It is fully compatible with mainstream deep learning frameworks, and open-source large models such as DeepSeek, Qwen, and STEP can be quickly migrated and deployed, reducing the cost of landing and adapting domestic compute chips. Because the chip, software, and cluster come from the same team, each generation does not require cross-vendor re-adaptation, and the operator optimizations and scheduling strategies accumulated in the previous generation can be directly reused in the next. The software-defined architectural attribute amplifies this advantage. Traditional AI chips have fixed hardware functions: when the chip is taped out, which operators are supported and what data paths exist are already burned into the silicon. With software-defined chips, the hardware's Tile array and data paths can be configured by software, and the same chip can execute different compute structures through different software configurations. Thus the focus of adaptation shifts from hardware to the software layer. For adapting a new model, the CAAP compiler only needs to map it into a dataflow graph and expand execution on the Tile array; core operators are already covered by the operator library, so only incremental optimization is needed. After a chip generation change, the hardware execution model remains consistent, and the compiler optimizations, operator implementations, and scheduling strategies refined for the previous generation can be carried over directly without rebuilding around new hardware.

In operations, "full-stack homogeneity + intelligent operations" lowers cluster operations costs. For clusters with heterogeneous hardware and mixed architectures, the workload of troubleshooting, tuning, and compatibility maintenance grows linearly with scale. Dongfang Suanxin's full-stack homogeneous technology system, combined with the intelligent scheduling, fault self-healing, and full-dimensional monitoring systems deployed on the cluster, enables a limited operations team to support stable operation of a 128-card cluster; the gap in operations efficiency will widen further once cluster scale reaches the thousands.

In supply chain, a fully domestic supply chain addresses deliverability. Routes that depend on advanced processes and overseas high-end components have expansion cycles constrained by external capacity and control lists. DF1000 relies on a fully domestic mature-process supply chain, is not subject to overseas technology controls, can expand capacity quickly, has a controllable delivery cycle, and offers secure and autonomous supply chain, enabling it to respond quickly to market demand for compute infrastructure. This is precisely the source of confidence for sprinting toward thousand-card-level clusters by year-end.

Of course, this route has its own costs. The yield of 3D stacking decays multiplicatively as the number of layers increases; the more layers and the greater the capacity, the more obvious the cost pressure, and yield is the ceiling for 3D stacking. Trading mature process for a performance window is essentially using engineering complexity to offset process-generation gaps. This trade is worthwhile under current industry-chain conditions, but it is not a free lunch.

03 Demand is in place, and near-memory compute enters a window for large-scale delivery

The route's advantages must ultimately be tested in the market, and the signals from the market are clear enough. According to data from the China Academy of Information and Communications Technology, in Q1 2026 domestic AI compute demand rose 417% year on year, while supply grew 128%; high-end chips have entered a seller's market, with cards hard to obtain.

On the demand side, two main forces are driving growth. The first is the deepening of IT application innovation: as the requirement for compute autonomy extends to core systems in finance, telecommunications, energy and other industries, the requirement for the compute foundation has upgraded from "usable" to "usable at scale." The second is the accelerated deployment of industry AI: large models are penetrating from internet companies into industry scenarios, and for reasons of data security and business latency, industry customers increasingly require private deployment for their training and inference workloads. These demands make cost-effective, scalable domestic compute a rigid necessity. More critically, the workload structure is also changing. Pretraining is concentrated among leading large-model vendors and national-level compute centers, while the larger increment lies in fine-tuning and inference of industry models. These workloads are insensitive to single-card peak specifications but more sensitive to total cost of ownership, delivery cycles and long-term stable operation—exactly where near-memory computing solutions excel.

On the supply side, Dongfang Suanxin's product tiers cover different scale requirements from a single card to a full cluster. The Dianfeng DF1000 accelerator card is the smallest delivery unit, the Qingyuan QY100 is an 8-card single-machine server, the Tuoyu TY64 is a 64-card liquid-cooled super node with 33 PFLOPS (BF16) of compute per node, and the Huisuan series covers 128-card, 256-card and 512-card clusters delivered as complete systems. The 128-card cluster system is running stably and has achieved large-scale training cluster delivery, with thousand-card-level cluster delivery to be achieved by the end of the year. The iteration cadence is also set: the DF2000 is planned for launch in Q4 this year with approximately 1,000 TFLOPS of BF16 compute and 15TB/s of memory access bandwidth; the DF3000 is planned for Q4 2027, with specifications doubling again on that basis.

For the domestic compute industry, the value of this route goes beyond one company. It offers a replicable paradigm: not relying on the most advanced process nodes and HBM, building on a fully domestic supply chain, and trading architectural innovation for system efficiency—low investment, fast deployment, iterable. As more and more industry workloads need to run on an autonomous and controllable foundation, the industrial space for this paradigm will open up further.

04 Conclusion

Looking back, running the full chain from chip to cluster in 24 months is a complete self-validation of the near-memory computing technology route: the efficiency advantages in the three stages of system-level verification, software adaptation and industrialized delivery ultimately converged into the result of "fully domestic training cluster delivery." Domestic compute has thus crossed the key threshold from parameter announcements to industrialization validation.

How far this route can ultimately go—Professor Wei Shaojun himself gave a restrained answer: the long-term ceiling of the entire software-defined near-memory computing route remains the process node. He acknowledged that if domestic advanced process technology achieves a breakthrough in the future, the company will be the first to adopt more advanced processes. The significance of this route is to win a time window for domestic compute, not to declare that process no longer matters.

Large-scale application after validation is the real test. From 128 cards to a thousand cards, each step up in scale brings pressures of stability, yield, operations and delivery organization at a different order of magnitude; real customers' business workloads are far more heterogeneous than the model combinations in trial training; and whether this route can continue to deliver on its performance promises over long-term evolution still needs time to answer.

For decades, the core question the domestic chip industry has answered has been "can it be built?"; three numbers suggest the industry's question has now changed to "can it be delivered, can it be used?" The time gap of years versus weeks between chips and algorithms cannot be closed by chasing single-point specifications. Dongfang Suanxin's route proves for the first time that it can be filled with system efficiency. When the pace of chip iteration begins to keep up with the pace of application updates, the mismatch between domestic compute and the evolution of the AI industry finally shows, for the first time, the possibility of being bridged.

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