Inside Intel's Fabs: Chips Head Toward 3D Stacking by 2045, Mass Production of New Structures to Take About a Decade

On October 23, the well-known tech podcast host Dwarkesh Patel released a new special episode. He spent two days touring Intel's fabs and research labs, speaking with five technical leaders, with topics ranging from gate-all-around and backside power delivery to CFET, and all the way to Intel's collaboration with Musk's Terafab project.

These conversations point to two judgments. Chips in 2045 will continue to grow in the direction of 3D stacking: transistors, wiring, and the connections between chips will all stack upward, but each new structure takes about a decade to work through heat dissipation and integration challenges, and engineers themselves have only about four years of visibility into the technology roadmap. The tighter constraint right now is equipment: the host mentioned that AI compute has grown 3x per year for a decade, and Intel's CTO estimated that existing global equipment is roughly only enough to double advanced-process wafer output.

Intel's R&D head: chips in 2045 will grow upward, and heat is an unavoidable cost

Chips compute via transistors. A transistor is a tiny switch, and its on/off states correspond to 1 and 0. Apply voltage to its gate, and the channel below conducts; remove the voltage, and the channel closes.

As devices shrink, the channel no longer closes tightly and current leaks through. The solution is to have the gate control the channel from more sides: planar transistors only press down from above, FinFET stands the channel up as a thin fin and wraps it on three sides, and gate-all-around cuts the channel into suspended thin ribbons, each wrapped fully around.

Chris Auth, who leads development of Intel's current volume manufacturing processes, said gate-all-around was already the known endpoint back in the 1990s: "Gate-all-around really is the ultimate transistor." The preceding steps were not skipped—strained silicon, high-K metal gate, and FinFET were all done in sequence—"you don't do it before you have to."

The next step is CFET: transistors in circuits come in N-type and P-type, appearing in pairs, and today they sit side by side; CFET stacks them vertically, fitting twice as many in the same area, at the cost of harder inter-layer routing and harder heat dissipation.

Chris believes that by 2045 the structures will be more aggressive. "Right now you're dealing with a transistor suspended in interconnect, and you think: why not transistors, interconnect, more transistors, more interconnect?" Memory chips already do this—NAND flash has 3D structures—and he believes DRAM will eventually get there too.

Heat dissipation is the biggest limit. He groups the factors limiting compute into three things: how fast the switch is, how much power the switch consumes, and how heat is dissipated. 3D devices make the heat problem more prominent: "This will be a limit, and it will always be a limit, but these are problems we can solve." As for when it lands, he is very conservative: "Our visibility into technology scaling is about four years. Beyond those four years, you feel you can do another four. But if you talk about ten years, it's hard to say what it will look like."

Above the transistors, more than a dozen layers of metal wiring must be stacked to connect them into circuits; this layer is called interconnect, and it currently uses copper. Jack Kavalieros and others in the research lab are exploring replacing it with ruthenium: copper wires need a liner layer first to adhere properly, and the thinner the wire, the larger the share of the cross-section the liner takes up, whereas ruthenium can be etched directly and needs no liner. They said: "At those very fine dimensions, if you can trade the resistance of the liner for no liner, ruthenium starts to win." The crossover point is around a 20-nanometer pitch. They also cautioned that the previous node chose cobalt and now it's back to copper: "The leading option then was cobalt, now it's copper again, and in the future maybe ruthenium."

The connections between chips were explained by Tyler Osborn, director of the advanced packaging technology development department. The episode's narration first points out the contradiction: when chip area doubles, edge length only doubles, and data exchange between chips happens along the edges. In AI computing, the speed of moving data often determines overall speed more than the computation itself.

Hybrid bonding is one solution: skip the solder bumps, align the copper interfaces of two chips directly, press them together, and apply heat so the interfaces bond, allowing contacts to be packed more densely. Tyler gave a set of numbers: 15 years ago the pitch of first-level interconnect was 130 to 150 micrometers; today's Foveros in volume production achieves 25 micrometers; in the lab it is already below 10 micrometers; and at this year's IEEE ECTC conference, a paper presented reliability data for hybrid-bonded devices with 0.45-micrometer pitch. His assessment: "I see a very long runway here."

New structures reach volume production a decade late; Intel sets a budget for innovation

FinFET was validated in the lab in 1989 and reached volume production in 2011; gate-all-around was validated in 1988 and only reached volume production in 2022, by Samsung—this is the timeline given in the episode. In between, about 2,000 process steps must be tuned to stability, repeatedly run at scale on wafers (round silicon slices from which chips are cut) every week, and yield (the proportion of good chips) must also meet targets.

Intel's lesson came from 10 nanometers (one generation of manufacturing process, called a node in the industry). Chris recalled that at the time the scaling pace far exceeded historical levels, and it had to be done without new tools, "which put a great burden on the process and the engineers." In his view, the technology that most should have been pushed back was EUV (extreme ultraviolet lithography): "When we started defining 10 nanometers, the conclusion was that EUV was not ready." EUV uses light with a wavelength of 13.5 nanometers to print circuit patterns onto wafers; the shorter the wavelength, the finer the lines that can be printed in one pass. The episode's narration laid out the outcome: 10 nanometers was originally scheduled for 2016 but only began manufacturing in 2018; TSMC put EUV into volume production in 2019, while Intel's first EUV process only produced products in 2023.

Intel's 14A external customer decisions are underway, and what customers value is predictable progress. Chris summed it up: "What we learned is, don't do too much innovation in one node, because the more innovation, the higher the complexity." To that end, Intel set up "stage gates": a new technology moves from pathfinding into development, and yield, defects, and performance must all meet the bar; if they don't, it gets pushed to the next generation.

The same pragmatism shows up in the fab's conference rooms. At the Hot Topics meeting, Kevin Fischer has to make the call when information is incomplete: "One of the things you learn is that you never have a complete data set. If you wait for a complete data set, you've waited too long, and it's already too late." What he has to judge is "how much risk are we going to take."

His example was "epitaxial nodules." Epitaxy is growing new crystal layers on the wafer surface one layer at a time; if it grows wildly in a local spot, it forms a bump that shorts adjacent areas and causes transistors to fail. The team worked "highly in parallel," trying multiple approaches at once—adding cleaning steps to remove the nodules while also hunting for the root cause. The highest-priority expedited lot is called HotBox 1, which gets priority on every tool. Kevin said: "Keep one carpool lane on the highway, everyone else get out of the way, and only this one experiment can run." The cost is that "it drags down the whole fab," so the fab people are reluctant to play that card.

In the research lab, new structures first get a "short flow" prototype: only a few key steps, and once measured accurately, they are assembled into complex devices. For example, CFET first gets a simplified version with one ribbon on top and one on the bottom, "which may not yet have an advantage over today's side-by-side nanosheets," but it can first verify the wiring problems after stacking. Materials are eliminated just as directly: a new material may be ruled out because it "won't stick," or gases in later process steps may change its properties, "and if we can't find a way to control it, for us that's a dead end."

Intel CTO: We need 3x the compute, but equipment only supports 2x

The host noted that ASML delivers fewer than 100 EUV lithography machines a year, which must be split among Intel, TSMC, SK Hynix, and others. Intel CTO Pushkar Ranade acknowledged this is a constraint, while saying "EUV, or ASML, is not the only bottleneck"—"we're seeing severe shortages across all equipment." Once a process is set, the equipment is locked in: "We can't just swap in a different tool to run the same process." His buffer is to keep equipment as common as possible between nodes: "From 18A to 14A, maybe 80% of the equipment can be reused."

When the host asked whether global equipment is enough to increase advanced-process wafer output tenfold, he replied: "Tenfold, no; about twofold, probably yes." The host pointed out that the AI industry has grown compute 3x per year for a decade, and Pushkar said that unless the entire supply chain produces more, output can't increase. The host summarized: "Output can increase within 12 months, but by 2030 it won't be much higher than current forecasts." Pushkar added the cycle time: equipment orders "take 18 months to arrive," which pushes into 2028, and then new buildings are needed, "basically toward the end of this decade."

Behind this is the cost structure of the foundry business. Pushkar said: "Once a fab is built, about 80% of the cost is fixed." The tracks and stations are paid for up front, and one more passenger adds almost no cost, so every extra point of utilization translates directly into revenue. He also attributed the industry's concentration to this: forty years ago there were twenty foundries, and now only three remain.

On catching up with TSMC, he believes what needs to be closed is scale: "What we need to catch up on is scale." "If you're talking about technology, I think we're already there, maybe a few percentage points behind on performance, power, or area density." Facing the SemiAnalysis comparison cited by the host, he said: "First, I don't agree with your benchmark." His standard is being on time: a few percentage points behind is acceptable, "but you have to be on time."

On capital expenditure, the host gave TSMC's figure of about $50 billion this year and Intel's about $20 billion (TSMC has already raised its 2026 capex to $60–64 billion). Pushkar considers the comparison unfair: TSMC is the foundry for almost everyone, while Intel mostly makes chips for itself, and spending will rise as external customers increase.

Terafab is one example of external pressure. Pushkar relayed Musk's thinking: "Either we build Terafab, or there are no chips." The host pointed out that tools are the bottleneck and that the total amount of silicon worldwide will not increase because of this; Pushkar responded that power, water, and consumables can be expanded, but "tools can't." He also said that the cost of building a fab doubles every 4 to 5 years, that a single High-NA lithography machine together with its supporting equipment costs about $400 million, and that this curve cannot extend indefinitely. He offered a thought experiment: let people eat hamburgers and smoke cigars inside a research fab and see what happens to yield. He admitted that no existing manufacturer is willing to do this: "This is a risk-averse industry."

At the end of the interview, the host suggested that Intel commit to purchasing tools in large volumes the way Nvidia locks up memory. Pushkar replied: "If we had known then what we know today, we would have invested more about a year ago. Knowing what we know now, I think we would invest more." He also mentioned the sale of the flash memory business: "Obviously, in hindsight, that wasn't the smartest timing." And he believes the supply gap in memory is larger than in compute.

The same High-NA lithography machine, two different calculations from Intel and TSMC

High-NA is an upgraded version of EUV, with the lens's numerical aperture raised from 0.33 to 0.55, so the feature size that can be printed in a single exposure is about 1.7 times smaller. When patterns are too dense, the machine cannot print them in one pass, so they must be split into two or three separate exposures, each taking machine time and adding another chance for defects. The narration did the math: one EUV machine costs about $200 million, and High-NA is about twice as expensive; whether it pays for itself depends on how many exposures can be eliminated.

Chris said the reason the two companies reach different conclusions about the same equipment lies in architecture. "We use backside power delivery, which means your spacing requirements on the front side are relaxed." Backside power delivery moves the thick power lines to the back of the wafer, leaving only fine signal lines on the front, so routing space is more generous and High-NA can print directly in one pass. He believes TSMC does not have backside power delivery, must use tighter spacing, and cannot use High-NA, so it can only continue with double-patterning EUV. "It's not very helpful for them, but it's very helpful for us." But this is Intel's side of the story.

What the market cares about right now is cost. TSMC Chairman C.C. Wei said at the shareholders' meeting in June that the reason High-NA has not yet entered mass production is purely cost, and in September there were reports that TSMC had agreed to use High-NA in mass production starting in 2030. Intel is keeping it as an option for 14A, and Chris said it will be discussed with customers one by one: "It has value, and it also adds complexity."

Intel now also makes chips for other companies (foundry), and must provide customers with a process design kit (PDK) that specifies what can be built with the process and under what rules. Chris acknowledged that for decades Intel only made its own products and had no formal PDK process: "18A didn't have a PDK at the beginning." It was added only after customer feedback, and 14A was built to this standard from the start. Risk disclosure and disclaimer

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