Peking University's Sun Zhong, together with IBM and a Silicon Valley team, publishes a review of modern analog computing

Simulation computing enters the matrix era! Peking University teams up with Silicon Valley's IBM to write a new definition

In a Nature-affiliated journal focused on unconventional computing, a review paper put "modern analog computing" in its title, attempting to establish a formal definition for this direction.

The work was led by Sun Zhong, a tenured associate professor at the Institute for Artificial Intelligence at Peking University, who is also slated to serve as chief scientist of the analog computing chip company Anna Zhixin.

Including Sun Zhong, the four authors come from Peking University, IBM Zurich Research Laboratory, and the Silicon Valley startup Unconventional AI, bringing together nearly all the most core forces in the current analog computing field.

IBM has been deeply engaged in analog computing and in-memory computing for more than a decade and is widely recognized in the industry as a benchmark; the paper's co-authors Manuel Le Gallo and Abu Sebastian are scholars at IBM Zurich Research Laboratory, and the latter is also an IEEE Fellow and a long-term core researcher in this direction.

At the same time, Silicon Valley companies working on analog computing are being frantically pursued by capital. Unconventional AI's valuation has already exceeded $4.5 billion, and Normal Computing has received investment from Samsung and Eric Schmidt. Both companies claim they can "reduce AI energy consumption to one-thousandth."

Sun Zhong has been trying to unify a direction. Two or three years ago he did the same thing in the in-memory computing field, when he likewise joined with international peers to write a paper titled "A full spectrum of computing-in-memory technologies," published in Nature Electronics.

He said the paper is only an opportunity; he wants to bring together several of the most core institutions in China and abroad to jointly write down the definition of "modern analog computing."

How to define "modern analog computing"

In this review paper, polished over several years, the four authors make the word "modern" the fulcrum of the entire framework.

When many people hear analog computing, their first reaction still stops at the old machines that were replaced by digital chips half a century ago.

To clarify understanding, the paper thoroughly distinguishes "modern analog computing" from "traditional analog computing" across three dimensions.

In the task dimension, traditional analog computing was aimed only at solving differential equations, while modern analog computing is mainly aimed at the matrix computations most in demand in the AI era and in 6G communications.

In the hardware dimension, traditional analog computing relied on CMOS analog circuits, while modern analog computing is rooted in new nanoscale devices such as resistive memory (RRAM and other memristors).

In terms of application feasibility, traditional analog computing was trapped by low precision and difficulty of scaling, while modern analog computing has explored an engineering path toward high precision and scalability, and uses a rigorous system to clearly define the boundaries, primitives, and evolution path.

The prerequisite for understanding this new system is to re-recognize the word "analog."

In the eyes of many people educated in modern engineering, digital computing represents "discrete," while analog computing is taken for granted to correspond to "continuous."

In his talk, Sun Zhong cited research by scholar Corey J. Maley published in WIREs Cognitive Science in 2024.

The research pointed out that the core concept of "analog" is not continuity but "analogy," that is, without going through binary symbolic abstraction, directly mapping a mathematical problem onto a physical system and relying on physical laws to naturally give the answer.

In everyday experience, shadows of analog computing are actually everywhere.

When a child learns arithmetic, one apple plus one apple equals two apples; for 3×5 multiplication, three piles of five apples each are put together and counted out as fifteen apples. These are all the most direct physical mappings.

Analog computing chips do the same kind of analogy; they try to find physical entities in microscopic circuits that can correspond to mathematical variables.

But in traditional integrated circuits, doing this runs into some obstacles.

In circuits, the physical quantities that can change in real time are usually only voltage and current, and once a resistor on a chip is manufactured, its resistance is a fixed, dead number.

If one wants to use Ohm's law to calculate multiplication, the two multiplicands of multiplication are always changing. One number can be input as a voltage signal, but if the other number becomes a fixed resistor, it simply cannot cope with dynamic computing tasks.

The key to breaking through this input limitation is to find a physical carrier for the circuit that can be rewritten at any time and can also remember values for a long time.

Resistive memory (also often called memristor) precisely provides this possibility. The core characteristic of this new nanoscale device is that its conductivity is not fixed; it can be precisely changed by applying electrical pulses, and the resistance value is not lost after power is removed.

This is equivalent to opening up, for integrated circuits beyond voltage and current, a new physical variable that can store in situ and be adjusted at any time: "conductance."

Thus, the two input numbers of multiplication have their own mapping anchors in the circuit: one number is directly programmed as the device's conductance value, and the other number is loaded as voltage across the device.

At the instant current flows through, according to Ohm's law, the output current magnitude is naturally the product of the two.

When the voltage-driven devices loaded on each row generate multiple currents that converge together into the same column wire, physical laws once again take over the computation. According to Kirchhoff's current law, the total current flowing into a node must equal the sum of the currents in each branch, so parallel currents naturally converge and add.

This means that a single multiplication relies on Ohm's law, while multi-path summation relies on Kirchhoff's law, and the multiply-accumulate result for an entire column is computed all at once at the instant the currents converge in the wire.

Combined with peripheral operational amplifiers to build closed-loop feedback paths, modern analog computing chips can further achieve equation solving.

Under the action of the negative feedback mechanism, after the circuit is powered on, it spontaneously converges to a physical equilibrium state within nanoseconds, and the stable voltage at that equilibrium point is, mathematically, exactly the solution to the equation.

In addition to the limitation of physical variables, traditional analog computing faces another fatal bottleneck: it simply cannot scale up.

In past schemes based on CMOS op-amp circuits, each operator required stacking a large number of transistors, resulting in extremely low area efficiency.

A 65-nanometer CMOS analog chip published in 2016 in the top integrated circuits journal JSSC had a considerable area but could accommodate only 4 integrators and 8 multipliers.

Moreover, analog voltage signals suffer severe attenuation when transmitted over long distances in circuits, and the area of CMOS operational amplifiers remains high, so integrating 1 million CMOS multipliers on a single chip is almost physically infeasible.

New memory devices have broken through this barrier. In a 1000×1000 micro resistive random-access memory crossbar array, 1 million natural multipliers can now be compactly integrated at high density.

The reason modern analog computing can break the deadlock in scalability still comes down to replacing complex CMOS analog units with new resistive memory devices.

A resistive device is essentially a two-terminal nanoscale element, only tens of nanometers in size. In physical manufacturing, engineers only need to lay 1000 metal row wires horizontally, have 1000 metal column wires cross over them vertically in three dimensions, and sandwich a layer of resistive material at each microscopic crosspoint where a row and column intersect.

A three-dimensional network of a thousand wires in each of the horizontal and vertical directions directly weaves out a full 1 million physical crosspoints within an extremely small chip area.

Each crosspoint has an independent conductance value; voltage is applied to the row wires and current flows out at the crosspoints. These 1 million nanoscale crosspoints are naturally 1 million parallel in-situ analog multipliers.

On the basis of this hardware generational shift, this review paper summarizes analog computing into three core primitives: solving differential equations, solving matrix equations, and matrix-vector multiplication (MVM).

These three share the basic set of operators—adders, multipliers, and integrators—and are tightly coupled at both the mathematical and circuit levels.

After discretization, differential equations can be transformed into matrix equations; matrix equations can be approximated through repeated iterations of matrix multiplication, or directly measured in one step through an analog closed-loop network. The three are interconnected and form a unified computational spectrum.

Sun Zhong said that merely using analog circuits in isolation to solve a specific equation or perform multiplication is not particularly novel. The original intention behind writing this paper was precisely to connect these scattered technical points, establish a complete system for modern analog computing, and define a clear direction.

What a GPU does in a hundred iterations, it does in one step

Defining a new system must be supported by disruptive measured technical results.

Sun Zhong and Anna Zhixin chose a path that is more technically challenging and more differentiated, starting from solving matrix equations and matrix inversion.

Behind this choice lies the biggest pain point for digital chips in the real world of computing power.

In the heavy workloads of intelligent computing centers and scientific computing, more than 80% of the computing overhead is often spent on solving linear equation systems of the form Ax=b.

Mathematically, the core of solving this equation is to compute the unknown vector x, and it is hard to avoid the hard hurdle of "matrix inversion."

And matrix inversion is precisely the operation that traditional digital chips fear most.

Compared with the relatively simple matrix multiplication, matrix inversion has extremely high computational complexity, usually reaching O(n^3).

Digital chips simply do not have dedicated hardware units that can directly perform matrix inversion. For a general-purpose GPU to complete one inversion, it can only use numerical algorithms to decompose it into dozens or even hundreds of matrix multiplications for repeated looping and gradual approximation.

This directly causes massive amounts of expensive computing power and time to be consumed entirely in lengthy iterative computation and data movement.

The analog matrix computing (AMC) circuit designed by Anna Zhixin changes the rules. The team introduced a global negative feedback closed loop around the resistive memory array, making the circuit's transient response directly correspond to solving the matrix equation.

An operation that originally required a GPU to perform hundreds of iterations can output an exact solution in one measurement with the AMC circuit, with a single operation taking less than 100 nanoseconds, and this physical response time is independent of the matrix dimension.

But no matter how fast the computation, if it is not accurate, analog chips still cannot leave the laboratory. Precision has always been the "Achilles' heel" preventing analog computing from becoming practical.

In 2019, when Sun Zhong's team demonstrated one-step solving of matrix equations in PNAS, constrained by fluctuations in analog devices, the relative error of the solution was about 3%, and the hardware array scale was only 3×3.

This technical problem, which had remained unresolved for many years, was not completely overcome until October 2025.

At that time, Sun Zhong's team published a breakthrough paper in Nature Electronics, proposing a set of analog matrix equation solving schemes that balance high precision and scalability.

Since continuous conductance states are prone to drift and cause inaccurate calculations, the team simply borrowed the bit-slicing concept from early digital computers, abandoning unreliable continuous states and instead adopting the 8 discrete conductance states fully validated in each device (equivalent to 3 bits).

By splicing together 8 3-bit array slices, the system achieved 24-bit fixed-point precision.

Low-precision inversion is responsible for setting the direction, while high-precision multiplication is responsible for gradually eliminating the residual; after only 3 iterations, the relative error of the solution was reduced to 10^-4, and it can subsequently converge to 10^-7. This level of relative error matches the FP32 single-precision floating-point arithmetic of digital processors.

Because bit slicing supports deep expansion, there is theoretically no upper limit to this improvement in analog precision; it can be continuously increased by adding more slices and iteration steps.

Facing larger-dimensional real-world problems, the team also designed the BlockAMC blocking algorithm, which progressively decomposes a huge matrix into sub-blocks that can be carried by the hardware array, completing inversion and multiplication in batches. In actual tests, it has successfully scaled to complex matrices of 512×512 dimensions.

Having solved precision, another engineering challenge followed closely: how this analog system could seamlessly be compatible with the existing digital world.

Sun Zhong and the R&D team are well aware that today's IT infrastructure is built entirely on the digital foundation. Making a pure analog chip isolated from the world has no commercial future; analog computing must operate in coordination with the digital ecosystem.

In Anna Zhixin's chip architecture, matrix operations are handled by dedicated micro analog cores, and the computation results are quickly converted by analog-to-digital converters (ADCs) into digital signals. Data transmission between cores and across chips uses digital channels, and nonlinear operators such as square roots and trigonometric functions are also handled by mature digital logic.

This collaborative approach is summarized by the team as "let matrices belong to analog, and let logic belong to digital."

With this mixed-signal route, the chip industry's most natural concern often falls on interface overhead.

Each analog core must perform digital-to-analog and analog-to-digital signal conversion (DAC and ADC) before and after. Won't the energy consumed by frequent conversion completely eat up all the energy saved by analog computing?

If one looks only at the energy distribution inside the analog computing module, DACs and ADCs do indeed account for the vast majority.

However, thanks to the design of the bit-slicing architecture, each sub-array only needs to process 3-bit data, and the peripheral circuits do not need to be equipped with high-spec ADCs of more than ten bits and high sampling rates at all; basic converters with 6 to 8 bits of resolution and a 10 MHz sampling rate are sufficient.

In chip design, relaxing precision and sampling rate specifications can greatly trade for lower power consumption and smaller chip area.

Therefore, even when all the overhead of front-end and back-end digital-to-analog conversion is included, actual measurements and evaluations still show that, at the same FP32 computing precision as digital chips, this analog matrix computing scheme still achieves throughput about 1,000 times that of a single NVIDIA H100 core and digital ASICs, and energy efficiency about 100 times theirs.

Not only does it hold an advantage in computing power metrics, but on the manufacturing and supply chain side, this architecture also avoids high foundry barriers.

To improve computing density, digital GPUs must continue to invest in advanced extreme ultraviolet lithography processes such as 3 nm and 2 nm, whereas resistive random-access memory can already be reliably manufactured on mature processes of 28 nm or even 22 nm.

Domestic wafer foundries have already caught up with international giants in the accumulation of mature resistive device processes, enabling the chip to be implemented with independently controllable production capacity, with a comprehensive cost advantage of about 10 times compared with mainstream GPUs.

With a foundation of 1,000 times throughput, 100 times energy efficiency, and one-tenth the cost, the commercialization of this technology points directly to the real-world scenarios where the industry is most hungry for linear equation solving and matrix inversion operations.

In the short term, Anna Zhixin expects to launch an actual demonstration within one year for embodied intelligence motion control and planning.

When robots perform high-dynamic motion control, they must solve complex dynamic matrix equations in real time. The microsecond-level solving capability of AMC circuits can free robot joint movements from jerkiness and make them smoother and more fluid.

In the medium term, Anna Zhixin is focusing on massive MIMO signal processing in 6G wireless communications.

The underlying logic of wireless signal detection is likewise solving channel matrix equations. In massive MIMO experiments for 5G-A and 6G base stations, the Peking University team has achieved zero-error restoration of the Peking University emblem image and the 256-QAM constellation diagram after only 3 iterations, and its bit error rate curve overlaps with that of the digital FP32 scheme.

In a longer-term plan of 3 to 5 years, the team aims to expand the chip to thousands of parallel analog cores, natively supporting second-order optimization training for large models.

Second-order optimization is theoretically faster to converge than traditional first-order optimization, but each step requires solving the inverse of the Hessian matrix. In the past, digital GPUs simply could not compute it, and model companies could only settle for the next best thing, using 5 matrix multiplication iterations to approximate it.

Once high-precision analog matrix inversion natively supported by hardware is put into use, the physical bottleneck in large-model training optimization will be alleviated.

This time, Silicon Valley and China define it together

In the fields of semiconductors and frontier computing, people have long been accustomed to a fixed script.

Silicon Valley is the first to get a new technology route working, and domestic teams then quickly follow up.

But on the track of modern analog computing, the plot is reversed.

The person leading the joint effort with IBM Zurich Research Laboratory and a Silicon Valley unicorn to define the entire direction and draw its boundaries is the Chinese scholar Sun Zhong.

In this direction, the founding paper came from his team, and the precision deadlock that has plagued the industry for decades was broken by him;

On the industry side, two unconventional computing star companies in Silicon Valley, each valued at several billion dollars, are also pursuing core routes that extend from his research.

Being able to take the banker's seat in this field that represents the future of frontier computing rests on hard-core strength in two dimensions.

At the academic level, in 2019 Sun Zhong, as first author, published research in PNAS on solving matrix equations in one step with resistive switching arrays, the first foundational paper in this direction.

His 2025 Nature Electronics paper, which overcame the precision bottleneck, set the highest readership record in the journal's nine years since its founding after going online.

The achievement was covered in depth by mainstream media, selected together with DeepSeek for the "Top 10 Domestic Science and Technology News of 2025," and went on to win the "Top 10 Advances in China's Chip Science 2025" and the "Industrial New Sprout Award." It was selected for the permanent exhibition of the 2026 Zhongguancun Forum and the Exhibition of Original Innovation Sources, and was also named "Best Academic Paper" at the 2026 China Computing Power Conference.

More convincing than academic honors is the industrial following from across the ocean.

Two pioneering computing startups in Silicon Valley that have received heavy bets from top-tier capital are both evolving their underlying technologies in sync with his research.

One is Normal Computing, founded by former Google Brain and Palantir team members, which taped out its thermodynamic computing chip CN101 in 2025 and has raised more than $85 million in cumulative funding, with investors including Samsung, Eric Schmidt's First Spark Ventures, and the UK's Advanced Research and Invention Agency (ARIA).

In the company's 2026 paper "Thermodynamic Natural Gradient Descent" published in npj Unconventional Computing and its subsequent work on second-order optimization, the core solving hardware used is precisely the closed-loop negative-feedback analog matrix inversion circuit.

In his presentation slides, Sun Zhong clearly compared the topologies of the two, annotating a line: "Another name, same circuit," demonstrating the high degree of consistency at the underlying hardware level.

The other is Unconventional AI, founded by former Databricks AI head Naveen Rao, whose announced seed-round valuation exceeds $4.5 billion.

One of the co-authors of this "Modern Analog Computing" review paper, Piergiulio Mannocci, worked closely with Sun Zhong at Politecnico di Milano in his early years and is now also a core scientific researcher at Unconventional AI.

While following the public talks of the Unconventional AI team, Sun Zhong noticed that the unconventional analog architecture concepts they advocate show a high degree of academic rapport with the academic views he has articulated over the years.

What is worth discussing is the mirror-image difference in the promotional framing of companies in the two places.

Domestic teams such as Anna Zhixin focus more on "increasing computing speed by 100 times"; under the objective environment of limited computing power resources, China's AI research and development has a more urgent demand for compressing model training and iteration cycles.

But whether the goal is saving power or speeding up, for analog chips to truly move from the laboratory to industry, both sides must ultimately cross the same life-or-death threshold—precision.

Just as the computer pioneer Richard Sutton revealed in "The Bitter Lesson," the development of analog computing over the past half century has also gone through painful lessons.

Past research often retreated to the limited value of low-precision hardware in locally fault-tolerant tasks, but the practice of industrial deployment has repeatedly proven that computing architectures lacking precision find it extremely difficult to gain a foothold in mainstream industry.

Therefore, high precision is a prerequisite for new computing architectures to move from the laboratory to industry. After the release of the high-precision work in 2025, discussions in international academia and industry about "high-precision analog computing" increased significantly, and the industry is gradually moving toward this pragmatic standard.

After this review was published, "Modern Analog Computing" will enter the citation chain of subsequent research as a formal term, and its definitional framework comes from Peking University, endorsed by joint signatures from Chinese and foreign industry, academia, and research.

For Sun Zhong, this is only the first step.

What he wants to see more is that when this direction grows into an industry in the next five to ten years, people look back at the original defining paper and see the name of a Chinese scholar on the author list.