Intel Executives Discuss Advanced Wafer Capacity and 2045 3D Chip Roadmap

As demand for artificial intelligence (AI) computing power continues to climb, capacity expansion in advanced wafer manufacturing is facing challenges such as equipment supply and manufacturing costs. Intel Chief Technology Officer Pushkar Ranade noted that, given the current global scale of semiconductor manufacturing equipment, expanding advanced-process wafer output tenfold would not be easy; by comparison, increasing it to about twofold is more realistically achievable.

According to a visit to Intel's wafer fab and an executive interview released on October 22 by the technology podcast "Dwarkesh Podcast," the bottlenecks in advanced-process development lie not only in chip design and process scaling but also in upstream supply capabilities such as extreme ultraviolet (EUV) lithography equipment, etching equipment, and thin-film deposition equipment. To further expand capacity, the equipment supply chain must grow in tandem.

The interview also extended its focus to chip manufacturing technology over the next 20 years, covering technologies such as Intel's 14A process, High-NA EUV lithography, backside power delivery, complementary field-effect transistors (CFET), and hybrid bonding, and exploring how wafer fabs can break through the limitations of existing manufacturing models.

Intel's 14A in development for over 3 years, seeking to avoid repeating the 10nm delay

Intel executive Chris Auth revealed that the 14A process has been in development for more than 3 years, and that a single advanced process involves about 2,000 manufacturing steps. Moving from R&D to mass production requires not only equipment configuration and process optimization but also defect control and yield improvement; it must be ensured that the process can be stably put into large-scale production.

Intel previously faced challenges due to delays in its 10nm process, caused by factors including overly aggressive targets for increasing transistor density and the simultaneous introduction of complex process innovations.

To reduce similar risks, the company now uses technology maturity assessments and phased review mechanisms to control the number of major innovations introduced simultaneously at a single process node, improving the predictability of mass-production timelines.

In lithography, High-NA EUV is one of the important technology options for 14A. This technology raises the numerical aperture from 0.33 to 0.55, improving single-exposure resolution by about 1.7 times.

Intel believes that, combined with backside power delivery technology, High-NA EUV is expected to reduce the multiple-patterning steps required for some complex patterns, but whether to actually adopt it will still depend on cost and customers' chip design requirements.

Backside power delivery is another important development direction. In traditional chips, power and signal routing are mainly located above the transistors; backside power delivery technology moves the power network to the backside of the wafer, freeing up frontside routing space, which helps improve power delivery efficiency, reduce interconnect congestion, and create conditions for continued scaling of advanced processes.

Transistors moving toward 3D stacking; new materials beyond ruthenium also draw attention

Looking toward chip manufacturing in 2045, transistor architectures may further move from planar arrangements toward true 3D stacking.

Intel is researching the CFET architecture, stacking N-type and P-type transistors vertically to increase transistor density per unit area. In the longer term, chips may adopt designs with multiple layers of transistors and interconnect structures stacked alternately, but heat dissipation, etching, material filling, and manufacturing costs remain challenges that must be overcome.

Metal interconnects inside chips also face material selection issues. When interconnect pitch shrinks to about 20 nanometers, the liner materials required for traditional copper interconnects take up more and more space, compressing the actual conductive area. Intel is therefore researching materials such as ruthenium (Ru), hoping to improve the effective resistance of extremely fine interconnect lines; however, in larger interconnect structures, copper will still play an important role.

Advanced packaging is another path to increasing chip integration density. Intel's Foveros technology has achieved a 25-micron interconnect pitch, and the company continues to research hybrid bonding technology below 10 microns. The interview also mentioned that academic research has demonstrated reliable results at a 0.45-micron pitch.

Hybrid bonding is expected to further increase connection density between chips, reduce power consumption for data transmission, and enable tighter integration of logic chips and memory, making it an important technology direction for future high-performance computing architectures.

Catching up with TSMC is not only about process; wafer fabs must also be redesigned

Speaking about competition with TSMC, Ranade argued that technological strength cannot be measured only by slight differences in transistor density, performance, or power consumption. Fab scale, yield, customer ecosystem, on-time delivery capability, and the ability to rapidly expand capacity are also important components of a foundry's competitiveness.

He believes that Intel is already technically competitive but still needs to catch up with TSMC in production scale.

On the other hand, the construction cost of advanced wafer fabs continues to rise, and investment in High-NA EUV and related equipment has reached the hundreds-of-millions-of-dollars level.

Ranade pointed out that the semiconductor industry cannot forever continue the manufacturing model of the past decades; it must re-examine cleanroom design, equipment configuration, process flows, and fab construction methods to find lower-cost, more efficient production systems.