Understand this story
On November 5, 2026, NVIDIA introduced the five co-design elements of Vera Rubin NVL72, including NVFP4, Wide-EP, Dynamo, the Vera CPU, and CMX. An article published by NVIDIA Developer on November 6 states that, with the per-GPU 288 GB HBM unchanged, the design achieves up to 30 times the per-megawatt throughput of GB300 NVL72 on SemiAnalysis AgentX. The article also states that NVFP4 reduces model footprint by about 3.5 times compared with FP16 and by 1.8 times compared with FP8, and that the NVFP4 KV cache is reduced by up to a further 50% compared with FP8; TensorRT-LLM's Wide-EP spreads experts across more than 8 GPUs, and Dynamo manages the KV cache as a cluster-level resource across GPUs, CPUs, and storage. There are currently no subsequent developments.
AI-generated from public reports
Latest development · Report
How NVIDIA Co-Design Maximizes the Value of Every Byte in the AI Factory: Five WaysDevelopments
1 confirmed developments
- Source:NVIDIA Developer · Generative AI
Reports and discussion timeline
Browse reports and discussion by time. Their evidence levels remain distinct.
Nov 6
NVIDIA Developer · Generative AIFirst-party
How NVIDIA Co-Design Maximizes the Value of Every Byte in the AI Factory: Five Ways
Through five co-designs—NVFP4, Wide-EP, Dynamo, Vera CPU, and CMX—NVIDIA enables Vera Rubin NVL72 to achieve up to 30x the per-megawatt throughput of GB300 NVL72 on SemiAnalysis AgentX while keeping 288 GB of HBM per GPU unchanged. NVFP4 reduces model footprint by about 3.5x versus FP16 and 1.8x versus FP8, and NVFP4 KV cache cuts it by up to another 50% versus FP8. TensorRT-LLM's Wide-EP spreads experts across 8 or more GPUs, while Dynamo manages KV cache as a cluster-level resource across GPUs, CPUs, and storage.