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Chester Lam reviews Prism binary translation performance loss

1 reports1 story updatesUpdated Sep 10 17:46

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Chips and Cheese author Chester Lam published a review on September 10, 2026, using Geekbench 7 to benchmark Windows 11's Prism binary translation, examining the performance loss of x86-64 programs on the Arm platform. Tests showed that x86-64 programs executed roughly twice as many aarch64 instructions after translation as native code, with every core showing performance losses of several generations. Testing was conducted on a Snapdragon X2 Elite Extreme X2E-96-100 laptop and on Neoverse N1 and N2 instances on Azure; even while bearing the translation loss, the Snapdragon's E-Cores and P-Cores still respectively outperformed Neoverse N1 and N2. The author also examined the translated code in C:\Windows\XtaCache, noting that Prism performs unnecessary register spills and splits 256-bit AVX operations into multiple 128-bit NEON instructions. This review is currently a single-source report with no subsequent developments.

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Benchmarking Windows 11 Prism Binary Translation: Performance Loss of x86-64 Programs on Arm

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  1. Chester Lam reviews Prism binary translation performance loss

    Source:Chips and Cheese

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Sep 10

  1. Chips and Cheese

    Benchmarking Windows 11 Prism Binary Translation: Performance Loss of x86-64 Programs on Arm

    Chips and Cheese author Chester Lam used Geekbench 7 to benchmark Windows 11's Prism binary translation, finding that x86-64 programs execute roughly twice as many aarch64 instructions after translation as they would natively, with performance losses of several generations across all cores. Testing was conducted on a Snapdragon X2 Elite Extreme X2E-96-100 laptop and on Neoverse N1 and N2 instances on Azure; even after bearing the translation losses, the Snapdragon's E-Cores and P-Cores still respectively outperformed the Neoverse N1 and N2. The author also examined the translated code in C:\Windows\XtaCache, noting that Prism performs unnecessary register spills and splits 256-bit AVX operations into multiple 128-bit NEON instructions.

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