Intel CTO says leading-edge wafer output can expand at most to two times, constrained by the semiconductor supply chain
Intel CTO Pushkar Ranade said on the Dwarkesh podcast that even with ample funding, global leading-edge wafer output would be hard to expand tenfold, and a more realistic upper limit is about two times. He noted the constraint comes from the entire semiconductor supply chain's ability to expand capacity in coordination, that ASML produces fewer than 100 EUV lithography machines per year and will struggle to expand output significantly by the end of this decade, and that Intel, TSMC, SK Hynix and other manufacturers all compete for these machines. He added that equipment ordered today is typically delivered about 18 months later, and capacity would only come online around 2028.
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Intel's CTO, starting from equipment delivery lead times and EUV lithography machine capacity, explained why advanced wafer capacity expansion is constrained by the entire supply chain.
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On October 23, in an interview on the Dwarkesh podcast, Intel Chief Technology Officer (CTO) Pushkar Ranade said that even with sufficient funding, global cutting-edge wafer output would be hard to expand tenfold, and a more realistic upper limit for growth is about twofold.
On the podcast, Ranade was asked "whether the world has enough tools to increase leading-edge wafer output by 10 times." In response, he said, "Not 10 times, but maybe 2 times, yes." He believes this limit stems from the ability of the entire semiconductor supply chain to expand production in coordination, rather than from any single link.
Among them, ASML produces fewer than 100 EUV lithography machines each year, and it will be difficult to expand production substantially by the end of this decade, while Intel, TSMC, and memory makers such as SK Hynix are all competing for these tools.
He further explained that equipment ordered today is usually delivered only about 18 months later, meaning capacity will land only around 2028. Newly built fabs also cannot automatically bring more wafers, and an important reason is that equipment supply cannot keep up.
Ranade explained that to raise output overall, equipment suppliers, their upstream suppliers, and even lower-tier sub-suppliers must all increase capacity in sync. In other words, if any link among lithography machines, key components, materials, inspection equipment, and fab construction is a bottleneck, the final output of advanced wafers will be hard to jump substantially.