Intel CTO says leading-edge wafer output can expand at most to two times, constrained by the semiconductor supply chain
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Intel CTO Pushkar Ranade said on the Dwarkesh podcast that even with ample funding, global leading-edge wafer output would be hard to expand tenfold, and a more realistic upper limit is about two times. He noted the constraint comes from the entire semiconductor supply chain's ability to expand capacity in coordination, that ASML produces fewer than 100 EUV lithography machines per year and will struggle to expand output significantly by the end of this decade, and that Intel, TSMC, SK Hynix and other manufacturers all compete for these machines. He added that equipment ordered today is typically delivered about 18 months later, and capacity would only come online around 2028.
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Intel's CTO, starting from equipment delivery lead times and EUV lithography machine capacity, explained why advanced wafer capacity expansion is constrained by the entire supply chain.
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10 月 23 日消息，在接受 Dwarkesh 播客时，英特尔首席技术官（CTO）普什卡 · 拉纳德（Pushkar Ranade）表示：即便资金充足，全球尖端晶圆产量也难以扩大十倍，更现实的增长上限约为两倍。
在播客节目中，拉纳德被问及“世界上是否有足够工具，把前沿晶圆产量提高 10 倍”。对此他回应称“不是 10 倍，但可能达到 2 倍，是的。”他认为这一限制源于整个半导体供应链协同扩产的能力，而非某个单一环节。
其中，ASML 每年生产的 EUV 光刻机不足 100 台，且到本十年末也难以大幅扩产，而英特尔、台积电以及 SK 海力士等存储厂商共同争夺这些设备。
他进一步解释，今天下单的设备通常约 18 个月后才能交付，意味着产能要到 2028 年前后才能落地。新建晶圆厂也无法自动带来更多晶圆，重要原因是设备供应跟不上。
拉纳德解释称，若要整体提升产量，设备供应商、其上游供应商以及更底层的子供应商都必须同步增加产能。换言之，光刻机、关键零部件、材料、检测设备与工厂建设等环节，只要有一处“卡脖子”，先进晶圆的最终产出就难以大幅跃升。