Synaptics Launches Astra SR200 Series Edge AI MCUs with Integrated 256 MB Custom DRAM

New Edge AI MCU Requires Custom DRAM Source: Semiconductor Industry Observer Published: 2026-10-22 17:26 MCU AI-generated poster The new MCU combines AI-native acceleration with integrated high-bandwidth DRAM scalable to hundreds of megabytes.

Microcontrollers (MCUs) continue to evolve, and now they have reached their next turning point: edge artificial intelligence. The new MCU brings cloud models into traditional MCU architectures, enabling a better understanding of edge AI.

Unlike traditional MCUs limited by on-chip memory and compute capability, Synaptics says its Astra SR200 series MCUs combine heterogeneous AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of megabytes. This enables larger AI models and richer multimodal workloads to run entirely on-device.

At the Synaptics Technology Day held in San Jose on October 20, 2026, CEO Rahul Patel called the SR200 an xMCU because it provides multiple compute dimensions on a single piece of silicon. He also described Synaptics as a processor company focused on edge computing.

John Weil, Vice President and General Manager of Synaptics' IoT and Edge AI Processor business, called the SR200 a new-generation microcontroller. He noted that the three core principles behind this design shift are: Synaptics chose this path to build edge AI devices with always-on low-power modes and the powerful compute capability of entry-level microprocessors.

Custom Compute for Edge AI

The SR200 is the industry's first chip to combine Arm Cortex-M85 and Cortex-M52 cores, integrating high-performance compute with up to 400 GOPS of AI acceleration, 256 MB of custom DRAM, vision and audio capabilities, and hardware-level security protection. This edge AI MCU integrates Synaptics' Torq NPU and Google Research's Coral NPU, providing strong support for CNN and Transformer workloads.

"Synaptics offers a range of Arm cores from ultra-low power to high performance. This enables engineers to precisely select the level of compute they need," Weil said. This, combined with the SR200's tiered memory architecture, is essential for integrating multiple modalities such as voice, vision, audio, motion and context awareness and responding in real time. We have invested a great deal of time and effort in achieving high performance and efficient compute at low cost and low power. At the same time, we have also invested heavily in a memory architecture designed to supply memory to the CPU and NPU more efficiently.

Multi-tier Memory

Traditionally, memory architectures have been designed to meet the needs of CPUs and NPUs. However, a closer look at many AI applications shows that they often do not fully utilize compute capability; instead, they devote a large amount of resources to memory interfaces.

This is why cloud infrastructure requires such massive memory capacity. In traditional microcontrollers, we once had only a few hundred kilobytes of memory. Later, a few megabytes of memory became common. And now, when we talk about memory, we usually speak in units of hundreds of megabytes.

The SR200's tiered memory architecture builds high-performance compute around an on-chip memory architecture. It also includes a custom DRAM interface with in-package memory, bringing HBM-like high-performance memory to microcontrollers.

This tiered memory architecture solves two problems. First, it efficiently supplies resources to compute cores. Second, the right amount of memory supports ultra-low-power, always-on AI processing. The memory is custom-designed to simultaneously handle and respond to processes for applications such as always-on listening.

"In the memory-constrained world we live in today, it gives design engineers the potential to build truly differentiated edge AI devices," Weil said. "No one else is currently talking about microcontrollers with this kind of tiered memory architecture and capacity reaching hundreds of megabytes."

Finely Tuned Power Consumption

The SR200 microcontroller combines high-performance compute and low-power characteristics, which is critical for developing battery-powered edge devices. The tiered memory architecture also plays a key role in enabling ultra-low-power operation. In addition, Weil added, supplying data to the neural network processor more efficiently can also reduce device power consumption.

The SR200 microcontroller is available in three pin-compatible models. The SR210 delivers 200 GOPS of compute speed and is suited for power-optimized always-on voice and sensing applications. The SR230 adds vision, display and optional audio capabilities on top of 300 GOPS, targeting mainstream multimodal devices. The SR250 delivers 400 GOPS of compute speed and features dual vision and display paths for demanding edge applications.

These microcontrollers are designed for next-generation AI wearables, battery-powered sensing devices, connected cameras, streaming players, and industrial vision and voice systems. According to Weil, their largest application area today is wearable electronics.

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