onsemi to Acquire Ferric for $600 Million as AI Chip Power Delivery Moves Inside the Package

onsemi Acquires Ferric for $600 Million as the AI Chip Power Supply Battle Spreads Inside the Package Source: Semiconductor Horizons Published: 2026-11-03 16:17 onsemi M&A generates poster The kilowatt-level power consumption of AI chips is forcing power supply from a motherboard accessory into an in-package component.

Recently, onsemi announced the acquisition of integrated voltage regulator (IVR) vendor Ferric for $600 million in cash, with an additional contingent cash consideration of up to $175 million based on the achievement of certain future revenue targets, bringing the total transaction value to as much as $775 million. On the same day, onsemi raised its 2030 AI data center revenue target by $500 million, bringing it to more than $3 billion.

Source: onsemi

What this deal reflects is a physical migration underway in AI chip power delivery architecture—voltage regulation is moving from the side of the motherboard into the interior of the processor package. Ferric's IVR technology integrates the power controller, power transistors, inductors and capacitors into a single package, reducing board footprint by 50% to 70% compared with traditional discrete voltage regulation solutions.

onsemi CEO Hassane El-Khoury's positioning of this technology trend is that as AI processor power consumption continues to climb, power delivery must move ever closer to the compute core to reduce losses, increase power density and speed up response to load fluctuations.

In traditional AI server power delivery architectures, current flows from the 54V bus through an intermediate conversion stage down to 12V or 6V, and finally is stepped down by multiphase Buck voltage regulators on the motherboard to the sub-1V voltage required by GPU or ASIC cores. This multi-stage lateral power delivery chain has been a mature solution for many years, but the growing power consumption of AI chips is pushing it to its limits.

The TDP of AI accelerator cards is advancing toward the kilowatt level. Intel has stated in its public technology roadmap that it plans to achieve a 5kW GPU package in 2027 with the help of Foveros-B advanced packaging. The TDP of Nvidia's highest-end Rubin model is reportedly up to 2.3kW.

Rising power consumption causes current to surge dramatically. At a core voltage of less than 1V, over a thousand watts of power consumption means over a thousand amperes of current, while the power delivery path on the motherboard from the voltage regulator to the chip's solder balls must traverse several centimeters of PCB traces. The greater the current, the greater the I²R loss along the path, leading to a larger DC voltage drop, slower transient response and aggravated voltage fluctuations. More troublesome is that GPUs generate nanosecond-level transient current spikes when switching compute loads, and the parasitic inductance of the lateral power delivery path amplifies the voltage droop, thereby limiting the maximum frequency at which the chip can operate or forcing the design to leave a larger voltage margin.

These problems compound, making the location of power delivery itself a design variable. Every millimeter of distance between the chip and the power module consumes power budget that could otherwise be used for computing. When the physical losses of the lateral path can no longer be solved by optimizing motherboard layout, moving the voltage regulator inside the package or beneath the chip becomes an inevitable choice for breaking through the power delivery bottleneck.

Ferric's solution is to move the voltage regulator from the motherboard into the package

Ferric's technology roadmap targets this physical contradiction. Its IVR integrates the power controller, power switches, inductors and capacitors into a compact package, enabling voltage conversion to take place inside the processor package or substrate, shortening the path from the regulator to the compute core from several centimeters to several millimeters. According to data cited in onsemi's acquisition announcement, this architecture reduces board area by 50% to 70% while delivering more power closer to the processor.

The shortened path brings considerable engineering performance. Ferric's latest-generation product, the Fe1767 Newport, adopts a dual-sided vertical power delivery architecture, delivering 145 amperes of current within 49.8 square millimeters, achieving a current density of 2.9 amperes per square millimeter and efficiency of up to 90.5%. More critical is transient performance: compared with traditional lateral power delivery, Newport reduces power delivery network impedance and transient voltage droop by up to 57%. Narrower voltage droop means the processor can maintain a more stable core voltage during load swings, without sacrificing operating frequency for safety margin.

Ferric has more than a decade of R&D accumulation in integrated voltage regulation and magnetic components in this direction, holding more than 40 patents. What onsemi provides is production scale, packaging capability and customer access, enabling this technology to move from customized solutions to a product line that can be delivered at scale. According to the roadmap published by onsemi, current shipments are still mainly processor-side power delivery; the vertical power delivery solution that feeds power from beneath the processor is expected to enter scaled mass production in 2027, while the IVR deeply integrated with the processor belongs to the next-generation technology layout.

Source: onsemi

The power delivery link is turning from a supporting component into a system definer

This acquisition confirms a structural change that is underway: power delivery for AI chips is turning from "a supporting component on the motherboard" into "part of the package architecture," and the competitive boundary of power supply vendors is accordingly expanding from discrete device parameters to in-package integration capability and collaborative layout with processor design.

In addition to onsemi's acquisition of Ferric, Navitas Semiconductor also completed its acquisition of Claros in October 2026, likewise incorporating IVR technology into its power delivery map from grid to xPU, explicitly pointing to vertical power delivery and embedded power delivery architectures. In Intel's roadmap for 5kW AI accelerators, integrated voltage regulators and vertical power delivery are key technology paths. ADI has also made large bets in the AI server power supply field. Multiple power semiconductor vendors are concentrating investment in the power delivery position "closer to the processor" within the same time window, validating a new industry trend: when single-chip power consumption enters the kilowatt level, the physical losses of lateral power delivery are no longer an engineering detail that can be absorbed by optimizing motherboard layout, but a system problem that needs to be redesigned at the package level.

Source: Intel

In this wave of collective shift, onsemi's acquisition of Ferric fills in the voltage regulation inside the processor package in its power delivery map from grid to core. Previously, its power device portfolio covered multiple levels from AC-DC to board-level DC conversion, but the voltage regulation link inside the processor package had always been missing. After acquiring Ferric, onsemi's reachable scope in the AI data center power delivery chain extends from the edge of the motherboard to the interior of the chip package. The raising of the 2030 AI data center revenue target to more than $3 billion reflects the potential incremental revenue brought by this extension.

Source: onsemi

In the past, power chips were merely standardized components on the motherboard, and suppliers only needed to deliver on time. But in the era of in-package power delivery, power supply vendors must intervene early in the early design stage of AI chips, jointly debugging substrate structures and thermal solutions with chip makers. This physical migration regarding the location of power delivery is pushing power supply vendors from obscure "supporting suppliers" to "core partners" deeply involved in chip system definition. When the limit of physical distance is broken, the future competition for the AI computing foundation will escalate from a performance contest of single devices to a system-level collaborative contest in which chip design and power delivery architecture are highly coupled.

This article is reproduced from media reports or online platforms and represents the author's personal stance or views. Our reproduction is solely for sharing and does not mean we endorse or agree with it. If the source is incorrectly labeled or your lawful rights and interests are infringed, please contact customer service promptly, and we, as a neutral platform service provider, will promptly correct, delete or handle it in accordance with the law. Comments No user comments yet Latest News More Related Recommendations

More agents, the better Intel looks 2026-11-03 16:35

Global phone shipments plunge 19%, revenue rises 3% against the trend 2026-11-03 16:28

Apple's robot is not on a humanoid path 2026-11-03 16:24