Houmo AI Completes Several-Billion-Yuan Series B Funding; M50 Chip Has Secured Over 150 Product Design Wins
According to informed sources, compute-in-memory AI chip company Houmo AI recently completed a Series B funding round of several billion yuan, with the funds to be used to expand large-scale delivery of the M50 and advance R&D on the M6X and the next-generation 3D CIM. The company disclosed that in less than a year of mass production, the M50 has secured more than 150 product design wins and serves over 100 customers, covering four directions: Agent Computer, intelligent mobile terminals, embodied robots, and edge inference. The M50 offers 160 TOPS@INT8 of compute, 150 GB/s of memory bandwidth, and typical power consumption of 10W; complete systems such as the Lenovo AI Host P7 preview edition have adopted it for local large-model inference.
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The funding information comes from informed sources; the article also provides the M50's design-win count, customer scale, and product deployment cases, which can be used to gauge the commercialization progress of edge-side compute-in-memory chips.
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In September of this year alone, nearly ten domestic edge-side AI chip companies announced the completion of new rounds of financing. The gaze of capital is shifting from cloud-based computing clusters to the chip inside phones, computers, and robots.
The latest large financing round comes from Houmo AI. According to people familiar with the matter, the compute-in-memory AI chip company Houmo AI recently completed a Series B financing round, with a single round amounting to several billion yuan, having completed multiple rounds of financing within the past year. This round saw heavyweight upstream and downstream industrial capital collectively betting, with state-owned capital and international investors joining in together, and multiple existing shareholders continuing to increase their stakes, further confirming the high recognition of Houmo AI's technology roadmap and commercial prospects by domestic and international capital markets, and it has become a consensus that Houmo AI leads the edge-side AI market. Behind the intensive capital backing is Houmo AI's accelerated delivery from technological breakthroughs to large-scale commercial deployment: at the just-concluded Houmo AI Ecosystem Partner Conference, the company disclosed that its edge-side large-model AI chip M50, less than a year into mass production, has already secured more than 150 product design wins and serves more than one hundred customers.
It is understood that this round of funding will be mainly used to expand the scaled delivery of M50, advance the research and development of the new-generation M6X and next-generation 3D CIM products, and continuously improve the software toolchain and industrial ecosystem, promoting the scaled deployment of edge-side AI in more terminal scenarios.
Compute-in-memory is not a new concept. Why has it been chosen simultaneously by capital and terminal manufacturers at this moment? And on what basis has Houmo secured successive capital injections in this track?
Capital turns to the edge side, compute-in-memory returns to the center of the table
The answer is first hidden in a set of shipment data. IDC data shows that in the first quarter of 2026, global edge-side/edge AI chip shipments grew 45% year-on-year, while cloud AI chip growth was only 12%. Capital and shipments move in the same direction; demand for edge-side AI chips does not rest merely in investors' expectations.
Industrial giants are also betting on compute-in-memory with real money. In December 2025, Nvidia reached a non-exclusive technology licensing agreement with AI inference chip company Groq and absorbed its core team, at a scale of about $20 billion. Less than a year later, in October 2026, according to The Information, Nvidia plans to invest in inference chip company d-Matrix, which adopts a digital compute-in-memory architecture; previously, d-Matrix had announced access to Nvidia's AI factory ecosystem through NVLink Fusion. From Groq to d-Matrix, Nvidia's successive moves send a clear signal: restructuring the relationship between storage and computing, compute-in-memory is becoming an important industrial direction in the AI inference era.
In past years, the main axis of large-model competition was on the training side—stacking compute, stacking GPUs, stacking clusters—and architecture-level compute-in-memory could hardly become the industrial mainline. Now the weight of inference is rising; why is it precisely now? There are three layers to the reason.
One layer is that models are becoming smaller and stronger. Taking the Qwen series as an example, to reach comparable capability, the scale required by Dense models was compressed to about one-eighth within 17 months, and MoE models were compressed to about one-sixth within about 6 months; the models that edge-side chips can carry rose from the 7B level in 2024 to the 120B level in 2026. The two curves move toward each other, giving large models a technical foundation for running on terminals.
One layer comes from Agents. Agents no longer merely wait for users to ask questions, but begin to continuously understand goals, call tools, and execute tasks. Response speed, data privacy, operating cost, and user controllability thereby become important, and more and more tasks need to be completed locally; terminals, too, change from devices that passively execute instructions into computing entry points that continuously produce and consume Tokens.
There is also a layer that is storage itself. Terminals have limited space, power, and cost, and chips must simultaneously improve computing efficiency, storage capacity, and memory access bandwidth within limited conditions; while under the traditional architecture that separates computing and storage, model parameters need to be moved frequently, and the larger the data scale, the more prominent the latency and energy consumption. Storage is also getting more expensive: according to TrendForce data, in the first quarter of 2026, general-purpose DRAM contract prices rose 90%-95% quarter-on-quarter, and are expected to rise another 58%-63% in the second quarter. When inference enters terminals, how to make data move less is as important as computing power itself—compute-in-memory, which places computing where the data resides, thus returns to the center of the table.
After the track returns to the foreground, what really matters is whose path is clear enough and can be validated by products.
Houmo AI's answer is SRAM-CIM. Since its founding in 2020, this Beijing-headquartered company has always taken SRAM-CIM as its root technology, placing part of the computing where the data resides. While industrial exploration of compute-in-memory has mostly concentrated on low-compute, ultra-low-power scenarios, Houmo chose the direction oriented toward high compute and edge-side large-model inference. According to data disclosed by the company, after adopting SRAM-CIM, the area of the core computing unit is compressed to about 30% of the traditional architecture, and operating power consumption is reduced to about 10%.
Behind this is a team with both academic and engineering strengths. Founder and CEO Wu Qiang holds a PhD from Princeton University in the United States, has worked at AMD and Meta, and served as CTO of Horizon Robotics; the core R&D team has published multiple compute-in-memory papers at top chip conferences such as ISSCC and completed more than 10 SRAM-CIM chip tape-outs.
The difficulty is that edge-side workloads do not have the same requirements for capacity and bandwidth: some workloads care more about how large a model can be accommodated, while bandwidth-intensive workloads represented by Dense models care more about how fast data can be supplied to compute. Houmo's approach is to form two paths on the same root technology: 2D CIM and 3D CIM. 2D CIM combines SRAM-CIM with memory configuration and targets larger capacity; 3D CIM introduces SRAM-CIM into the stacked logic compute layer, deeply integrating the compute architecture with advanced packaging, targeting greater bandwidth while also alleviating the heat dissipation pressure of 3D stacking.
Both paths point to the same goal: continuously improving Token/$ and Token/W. The former concerns the bill of materials for a device, while the latter concerns whether it can run stably for a long time within limited battery, heat dissipation, and space. In other words, these two ratios determine whether a local large model is a demo or a business.
The paths must ultimately land on chips. The already mass-produced M50 has 160 TOPS@INT8 compute power, 150 GB/s memory bandwidth, and typical power consumption of 10W; the first 3D CIM chip, A20, has entered production, and the new-generation M-series product M6X is under development. Board-level products cover PCIe standard cards and miniaturized modules such as M.2 and MXM. The combination of chips, modules, standard cards, and multi-chip systems addresses the localization needs of running models ranging from the 8B level to nearly one thousand B level.
Less than a year after M50 mass production, more than 150 design wins have entered the edge side
Recently, at the CSDN 1024 Programmer Day and AI Builder Conference, the preview version of Lenovo's AI Host P7 made its debut. This palm-sized host, weighing only 300 grams, uses Houmo Intelligence's M50 for local large-model inference. The M50 provides 160 TOPS of compute at 10W typical power consumption, and the whole machine's maximum power consumption is controlled at 30W, so an ordinary power bank can supply power. The P7 preview version can run large models with up to 125B parameters locally and supports continuous task execution 24/7, with data never leaving the device. Lenovo summarizes the goal of this device as helping developers and professionals in the Agent era achieve "Token freedom."
The P7 is not an isolated case. The Great Wall N90 Pro laptop can run a 35B-parameter model locally, bringing local large models into mobile office scenarios; UGREEN's Home Agent HA100 Pro combines local AI capabilities with NAS storage and smart home devices.
However, what explains the situation better than any single device is the number of design wins. In less than a year of mass production, the M50 has already obtained more than 150 product design wins, covering four major directions: Agent Computer, intelligent mobile terminals, embodied robots, and edge inference. For a chip company, a design win means the chip has been written into a customer's product plan, which demonstrates delivery capability better than a launch event.
The window is also opening. IDC predicts that in 2026, global shipments of generative AI phones will reach 432 million units, and China's AI phone shipments are expected to reach 147 million units, a year-on-year increase of 31.6%. NVIDIA this year released the RTX Spark PC built specifically for personal agents, with AI compute reaching 1 Petaflop and 128GB of unified memory; the first batch of AI laptops officially went on sale in mid-October, and can run a 120-billion-parameter large model locally. As giants turn Agent compute into mass-produced devices, the market space for edge-side AI is being confirmed at an accelerating pace. Terminals have limited power, space, and heat dissipation conditions, and chips that can stably produce more Tokens at lower power consumption are closer to scale.
Design wins answer whether it can be sold; the next question is whether it can be replicated. As projects go from one to one hundred, the focus of ecosystem building also changes. Over the past few years, Houmo has continuously improved the Dadao software stack around ease of use; common problems encountered in more than 150 product design-win projects have also continued to drive Houmo to fill in software and development support capabilities. On this basis, Houmo Intelligence has open-sourced the "Houmo AI Ecosystem Software," distilling model adaptation, compilation optimization, and development experience into reusable development support to reduce partners' repeated adaptation investment. The related open-source projects will be launched successively before January 2027. Design wins prove it can be sold; open source determines whether it can be replicated at low cost by more partners.
Technology, industry, and capital mesh together, and the edge-side Token flywheel begins to turn
Returning to this round of financing itself. If the heat of the track explains why capital is flowing to the edge side, the structure of investors answers why it is this company: upstream and downstream industrial capital often enters with scenarios; the simultaneous appearance of state-owned capital and international investors shows that this judgment has formed an intersection among different types of funds; and the continued increase in investment by multiple existing shareholders is recognition of past delivery.
Putting these together, the outline of a flywheel gradually becomes clear: the path proves the direction is valid, design wins and devices prove it can be monetized, and open source proves it can be replicated. Each new design win accumulates experience for the software, more mature software in turn lowers the adaptation investment for the next partner, and capital continues to be invested in scaling and next-generation products.
As the scale of models that can be carried on the edge side continues to rise and AI terminal shipments expand, chips that can stably produce Tokens at lower power consumption are expected to move from an option to a standard configuration for terminal manufacturers. By then, the standard for measuring an edge-side chip may no longer be just peak compute, but also how many Tokens it can produce per watt and per yuan. From the backing of several billion yuan in capital and product deployment with more than one hundred customers to the continuous iteration of the compute-in-memory architecture and the open-sourcing of the software ecosystem, Houmo Intelligence is forming a development flywheel driven by technology, industry, and capital. According to the company, its goal is to bring large models into every terminal and make human life better through innovative chip architecture.