Tohoku University and Aisin Unveil the World's First 16nm AI SoC with Integrated STT-MRAM

World's first STT-MRAM AI chip boosts energy efficiency by 50 times Source: Bandaozongheng Published: 2026-11-03 11:32 AI chip technology advances Generate poster Without DRAM and SSD, edge AI is breaking the memory wall with non-volatile memory.

Recently, Tohoku University of Japan and Aisin jointly released the world's first 16nm FinFET AI SoC with integrated STT-MRAM. This chip directly integrates 32MB of embedded STT-MRAM on-chip, storing all operating system boot data and AI model weights in non-volatile memory, completely eliminating the need for external DRAM or SSD in the AI processing flow.

The core data in the announcement shows that from power-on to operating system boot takes only 65.7 milliseconds, 38.59 times faster than the traditional approach; AI processing time is shortened to about one-tenth of the original, and the overall system is 25.2 times faster; the per-frame energy consumption of Tiny YOLOv3 object detection is 50.7mJ, only 1/50 of the traditional solution. This means that without relying on external storage, edge AI chips can also achieve millisecond-level instant response and extremely low energy consumption.

Data movement in traditional AI SoCs: high power consumption and long latency

In traditional edge AI SoCs, AI model weights are usually stored in external Flash. After the chip powers on, the weights must first be moved to DRAM, and then sent from DRAM to the AI accelerator for computation. Operating system boot also relies on external storage: the U-Boot and kernel images must be read from SSD or Flash into DRAM before they can run.

This path has two problems. First, the round-trip movement of data between external storage and compute units generates considerable latency and energy consumption. Second, DRAM is volatile memory and has leakage current during standby, so the chip consumes static power even when idle. For edge devices such as automobiles, robots, and industrial cameras, where power supply and heat dissipation are constrained, these two problems directly slow down the rollout of AI functions and affect continuous operation capability. In their joint press release, Tohoku University and Aisin described this as follows: the memory access and external data transfer brought about by the growing capacity of AI models are becoming the main bottlenecks reducing processing speed and energy efficiency.

The non-volatility of STT-MRAM shortens the physical distance between memory and compute

The traditional solution requires first initializing DRAM and then moving the boot image from SSD; it takes about 2535.3 milliseconds from power-on to kernel boot. This chip's solution is to replace the storage medium itself. It uses the resistance state of magnetic tunnel junctions to store data, so information is not lost after power-off, standby leakage is extremely low, and it also offers relatively fast read/write speeds and endurance close to SRAM.

Aisin and Tohoku University integrated 32MB of STT-MRAM directly on the AI SoC die, taking on two tasks previously performed by external storage: storing AI model weights and storing operating system boot data. This new solution reads boot data directly from on-chip STT-MRAM, compressing the time to 65.7 milliseconds. At the same time, in the AI processing stage, weight data no longer needs to be relayed from Flash through DRAM; the AI accelerator can directly read the on-chip MRAM nearby, so AI processing time is shortened by 10.16 times.

In addition, to run Tiny YOLOv3 within the limited 32MB on-chip capacity, the research team made two architectural adjustments. The first is an 8/16-bit hybrid multiplication architecture, allowing computations with different precision requirements to use different data bit widths. The second is weight sharing technology, reusing the same weight data across multiple compute units to reduce on-chip storage pressure. The chip itself also integrates an Arm Cortex-A53 dual-core CPU and a Mali-G31 GPU, giving it complete host control capability beyond the AI accelerator and enabling it to run an operating system and application software independently.

In the past, selection criteria for edge AI chips focused on TOPS and energy efficiency ratio, but these two numbers are usually measured under ideal data supply conditions. The first problem real devices face is startup: the time from power-on to outputting the first frame of detection results for an industrial camera directly determines whether the system can react at the moment an event occurs. The second problem is energy consumption during continuous operation: if the energy consumed per frame of detection is high, battery-powered mobile devices must either shorten battery life or reduce detection frequency. The 65.7 ms startup and 50.7mJ/frame provided by this chip precisely address these two real bottlenecks.

From an industry chain perspective, STT-MRAM has previously appeared more in independent memory research and embedded storage scenarios in automotive MCUs, and its combination with high-performance AI computing is not common. This SoC pushes STT-MRAM capacity to 32MB while taking on both OS boot and AI weight storage, meaning that the capacity and reliability of embedded non-volatile memory are crossing the threshold needed to support edge AI workloads.

For manufacturers also exploring near-memory computing and in-memory computing, this is a technology route parallel to HBM-PIM and LPDDR stacking, except that it targets not the high-bandwidth scenarios of data centers but the rigid demand of edge devices for "instant startup, extremely low standby energy consumption, and no dependence on external storage."

When the storage medium changes from volatile to non-volatile and the storage location moves from board-level external to on-chip proximity, evaluation metrics such as AI SoC startup time, per-frame energy consumption, and system complexity will all be comprehensively rewritten, and this chip has already provided a reusable benchmark. What is worth observing next is whether the 32MB on-chip MRAM capacity can support more complex models, and whether this architecture can reproduce the same high energy efficiency in scenarios beyond automobiles and robots.

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