Designing a 6-Layer 4-Channel ADC Board Using SuperEDA2 and Claude Code
SuperEDA2 is an MCP server that lets Claude Code design KiCad 10 schematics and circuit boards, and writes the reason for each design decision directly into component, net, and copper layer fields. The author gave only this one instruction, without specifying part numbers, circuit diagrams, or component counts, and the final design generated 281 components, 6 layers, 100×100 mm, 2054 traces, and 434 through-holes, with 0 schematic ERC errors and 0 PCB DRC errors, unconnected items, and schematic mismatches. The board carries four AD9254BCPZ-150 (14-bit/150 MSPS), ADA4932-1 differential amplifiers, CDCLVD1204 clock distribution, and a buck circuit plus six LDOs. This article was compiled from hackster.io.
Why read this
AI score 59
The original article fully presents the process and final design metrics of designing a 6-layer ADC board with Claude Code via an MCP server, serving as a reference case for AI-assisted hardware design.
Topics
Body · AI translation
What is SuperEDA2?
SuperEDA2 is an MCP server that allows Claude Code to design KiCad 10 schematics and circuit boards, and to implement those designs "as-is." Specifically, the reason for every design decision is written directly into the components, nets, and copper pours, rather than relying on an external database or notes tucked away in a file corner. For example, the reason for R101 is recorded in the R101 field, the reason for the GND pour is recorded in that pour's field, and the reason for inner layer In1.Cu is recorded in that layer.
For example, the following text is annotated on inner layer In1.Cu:
GND pour (full plane). Serves as the reference plane for the analog signal traces on F.Cu, and also as the electrode that electrically isolates F.Cu from In2 (digital bus). Routing signals here would break this isolation, so traces of other nets must not enter.
All 281 components and 265 nets each record the reason for their existence. Since no information points to content stored elsewhere, the next AI to touch this board—the AI after "compression," or an AI in another session—will know why a given part exists the moment it touches it.
This is what the whole concept means, and it is all that SuperEDA2 does.
The above was the entirety of the initial instruction. I did not specify specific part numbers, a circuit diagram, the number of components, or how to use each layer.
Schematic generated by SuperEDA2 / Claude Code, re-laid out by AI for improved readability. The netlist is exactly identical to the original design, containing 4 identical channel modules, power, clock distribution, and DE10-Nano pins. 281 parts in total, single-page file. ERC errors: 0.
Final result
• Size: 281 components, 6 layers, 100×100 mm, 2,054 traces, 434 vias
• Schematic: 0 ERC errors
• PCB: 0 DRC errors / 0 unconnected / 0 schematic mismatches
Both the schematic and the layout are complete. ADC: four AD9254BCPZ-150 (14-bit/150 MSPS); differential amplifier ADA4932-1; clock distribution CDCLVD1204; power: one buck circuit + six LDOs. None of the above was specifically specified.
Components are laid out by functional module
Components are not placed randomly: each functional module has a designated area, and components are placed within that area. The area occupied by each module and the components belonging to it are recorded in the PCB file in the form of [AI:module].
This article was compiled from hackster.io