NVIDIA lowers HBM and NVLink bandwidth on Rubin GPU systems, network bandwidth increases
In its October documentation, NVIDIA lowered the HBM and NVLink bandwidth of its Rubin GPU systems, while scale-out network bandwidth increased. The HBM4 memory bandwidth of the Vera Rubin superchip dropped from 44TB/s to 38.5TB/s, NVLink bandwidth fell from 7.2TB/s to 6TB/s, and scale-out network bandwidth rose from 0.8TB/s to 0.9TB/s. For the HGX NVL8 system, HBM memory dropped from 2.3TB at 176TB/s to 2TB at 130TB/s, and NVFP4 and FP8/FP6 training compute was also lowered, while bidirectional network bandwidth increased from 1.6TB/s to 1.8TB/s. Lowering the bandwidth threshold is expected to allow more HBM4 memory to meet Rubin GPU requirements, thereby increasing final yields.
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Comparing the two official documents shows the bandwidth trade-offs in the Rubin system, allowing readers to understand the magnitude of the spec adjustments and capacity considerations.
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NVIDIA lowers HBM and NVLink bandwidth for Rubin GPU systems, network bandwidth increases
2026-10-26 11:26 IT Home - Su Bo (Intern)
IT Home, October 26 news: According to a comparison between NVIDIA's first-party documentation from October of this year and third-party archived documentation from June of this year, NVIDIA has lowered the HBM and NVLink bandwidth of Rubin GPU systems, but network bandwidth has increased.
The HBM4 GPU memory bandwidth of the Vera Rubin superchip was previously 44TB/s and is now 38.5TB/s; the NVLink bandwidth was previously 7.2TB/s and is now 6TB/s; the scale-out network bandwidth was previously 0.8TB/s and is now 0.9TB/s. These figures are reflected roughly proportionally in Vera Rubin NVL4 and Vera Rubin NVL72, except that the scale-out network bandwidth of Vera Rubin NVL4 has increased from 0.4TB/s to 1TB/s.
As for the non-superchip Rubin GPU SMX module solution, the HBM memory of the two HGX NVL8 systems has dropped from 2.3TB 176TB/s to 2TB 130TB/s, the NVFP4 and FP8/FP6 training compute power have both been lowered, the NVLink Switch bandwidth has dropped from 28.8TB/s to 24TB/s, and the bidirectional network bandwidth has increased from 1.6TB/s to 1.8TB/s.
Lowering the bandwidth threshold is expected to allow more HBM4 memory to meet Rubin GPU requirements, thereby increasing final production yield.
In addition, the memory specifications of all Vera CPUs have been adjusted from 1.5TB LPDDR5X per chip to "up to" 1.5TB LPDDR5X.