Groq plans to adopt 3D stacked DRAM for its next-generation LPU

On October 21, 2026, reports said Groq plans to abandon reliance solely on SRAM in its next-generation LPU and switch to a 3D stacked DRAM architecture to increase chip storage capacity and adapt to ever-growing large model demands. The existing Groq LPU uses 500MB SRAM and 150TB/s bandwidth, providing about 1.20 PFLOPs FP8 compute per chip; the LPX rack is configured with 256 chips, totaling 128GB SRAM and 640TB/s scale-out bandwidth, and has been in full mass production since August this year. The next day's report further said that Groq, which has been substantively acquired by Nvidia, is evaluating the introduction of a 3D stacked DRAM packaging technology called 3DS in its next-generation chips, using TSVs to drill thousands of microvias inside DRAM chips for vertical interconnection; unlike HBM, which pursues data exchange rates, 3DS focuses on storage capacity expansion while maintaining the existing DRAM standard interface protocols. The report said the SRAM capacity that Groq's LPU architecture relies on is extremely small, creating a capacity bottleneck when facing models with hundreds of billions of parameters, and 3D stacking is intended to solve the problem of not being able to store enough while maintaining speed advantages. There is currently no official confirmation or subsequent progress.

AI-generated from public reports

1. Report date Oct 21· 2 reports

   Groq plans for next-generation LPU to adopt 3D stacked DRAM

   Source:Jiwei.com