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periment: Qwen-3.6-35B-A3B inference Setup In kicking off the experiment, I gave Claude Code with Fable 5 access to the paper and the MetaInfer Repository, as well as access to an NVIDIA B200 workstation via SSH. I told it the target hardware and provided a link to the Hugging Face repo for both the NVFP4 quantized weights I wanted to use for Qwen-3.6-35B-A3B, as well as the original full-precision weights to be used as an accuracy oracle. The agent was also able to deploy engine candidates to B

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be done in parallel, on a SonK cluster, or sequentially, if the provider wanted to take the nodes back and re-provision them); Blackwell, not Hopper (B200, B300, GB200, GB300) for NVIDIA, or MI355X for AMD are considered acceptable. H100 is now over 4 years old! We tested the cluster through 3 phases, described below. Of course, we always complement this testing by contacting customers of all these providers and taking their feedback into account. Phase 1: Audit First, the Audit covers yes/no qu

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re easier to serve. Using multiple processors together requires an interconnection network (interconnect) for communication. The lowest latency, highest bandwidth interconnect for Nvidia GPUs is NVLink. NVLink operates across a group of processors in a “domain” of some size. A single host operating system can support an NVLink domain of up to 8 GPUs. The largest NVLink domains that are generally available comprise 72 accelerators (in a multi-node IMEX domain). Using more accelerators would requi

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running voice agents with their own customers: Salesforce, Zocdoc, SAP, telli. Pipecat's lean toward companies that build tooling or reference architectures for other developers: NVIDIA's Blueprint, AWS, Anthropic 3. Can I get a working agent going today? When evaluating each framework it's important that you can easily build (and reason about the code for) a voice or video agent. Given AI-augmented development, a developer should be able to get an agent working in a day with either. Independen

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arning with Verifiable Rewards (RLVR) Again, the Mac is mostly the environment here and not the machine for running or updating the model during training. The model likely sits on NVIDIA GPUs and is fed via API to said Mac. By the way, NVIDIA’s CEO mentioned that GPT-6 Astra was being trained on 100,000 Grace Blackwell GPUs. 1.4 GPT-6 Astra is still a reasoning model The focus on computer-use training discussed in the previous section is not a fundamental paradigm shift in the training pipeline.

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ks It won't kill you, or humanity, to get off the AI upgrade treadmill New models arrive so fast, we already have more new tech than it's possible to understand in a career Cisco, Nvidia team up to build fatter, faster pluggable If you thought 1.6 Tbps was fast, just wait, Cisco's USFP targets 12.8 Tbps in a single optical pluggable TOP STORIES Anthropic asks users to stop being mean to Claude; '123456' password linked to Denmark data breach affecting 8.8M people; Microsoft and Anthropic play in

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Middle: How Language Models Use Long Contexts, TACL 2023 / arXiv:2307.03172; Thariq Shihipar — The New Rules of Context Engineering for Claude 5 Generation Models, Claude, July 24, 2026; Boris Cherny and Diana Hu — Boris Cherny: Building Claude Code, Y Combinator Startup School, July 27, 2026; Xiaoyu Zhang (BBuf) — AI-Infra-Auto-Driven-SKILLS, GitHub; Tianyu Zhang, Yusong Gao, Yun Zhang — Pushing the Limits of Serving DeepSeek-V4-Pro on Compute-Constrained NVIDIA H20, LMSYS Org, August 19, 2026

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type — you can use the library directly for academic or industry work without adopting SGLang's runner stack. SGLang will continue to develop the mechanism, and we expect the standalone library and the in-tree implementation to converge over time. Acknowledgments This work was a collaboration between the SGLang team and the Meta team. Meta: Shiyang Chen , Lianmin Zheng We also thank the NVIDIA, AMD, Thinking Machines Lab, and Meta PyTorch teams for their help along the way. ( Equal contribution)

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rainer("lerobot local") returns a Trainer that works like create policy() , and a TrainSpec describes the run; the record-train-deploy loop then closes in a few lines: On a single NVIDIA L4 ( g6.4xlarge ), 500 optimizer steps of ACT (51.6M parameters, effective batch size 8) over a 120-frame episode completed in 133 seconds and wrote a checkpoint that create policy() loads back through the same entry point used to run any other policy. Training time scales with dataset size, batch size, and step

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ks It won't kill you, or humanity, to get off the AI upgrade treadmill New models arrive so fast, we already have more new tech than it's possible to understand in a career Cisco, Nvidia team up to build fatter, faster pluggable If you thought 1.6 Tbps was fast, just wait, Cisco's USFP targets 12.8 Tbps in a single optical pluggable TOP STORIES Anthropic asks users to stop being mean to Claude; '123456' password linked to Denmark data breach affecting 8.8M people; Microsoft and Anthropic play in

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ree settings called reasoning-off, regular, and medium-effort, analogous to DeepSeek V4 in the previous section. Medium-effort is the cheaper reasoning mode compared with regular. NVIDIA introduces this mode during SFT using examples generated by GPT-OSS-120B in its medium-effort mode, and then further optimizes it during RLVR. About 2.5% of the RLVR prompts use medium-effort (this corresponds to length-based adjustments applied to their rewards). 6.2.1 Using Nemotron reasoning budgets during in

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en in Figure 14). Let's decode the name of the kernel: fmha (fused multi-head attention): All the primitive ops in attention is "fused" in one op now. cutlassF : built on CUTLASS (NVIDIA's open-source templates for tensor-core GEMMs), F for forward. bf16 aligned : runs in bfloat16 (no FP32 upcast, unlike math). 64x64 : the tile size. rf (register file): the working set is kept in registers, the fastest memory on the chip. sm80 : compiled for Ampere (the A100's compute capability 8.0). This is th

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of the more copied ideas after DeepSeek-R1. Qwen swaps standard quadratic attention for a linear network on every other layer, cheaper and longer-context, at some cost to quality. NVIDIA goes furthest, replacing the transformer on a fraction of its layers with state-space models that scale linearly and compute faster, keeping enough transformer layers to hold accuracy up. With architecture-level changes like these, the ladder reaches roughly a hundred and forty users per GPU. Nothing here is fre

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y side on the same machine without having to switch manually back and forth between models Regarding the second point in the list above, that Qwen models work better in Qwen-Code, Nvidia’s Polar: Agentic RL on Any Harness at Scale paper (May 2026) has a benchmark showing that the Qwen3.5-4B base model has the best coding performance in said Qwen-Code harness (both before and after their Polar-RL training), which I included below. The benchmark in the table above is for an older Qwen3.5 model, an

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xts. That being said, 120B-A12B may be a bit too large for local inference on regular consumer hardware, but there is a Nemotron 3 Nano (4B) version as well. Note that 2 days ago, Nvidia also released a scaled up-version of this, Nemotron 3 Ultra (550B-A55B), which scales the embedding and projection dimensions but otherwise uses the same building blocks. If you are interested in a visual, I posted about it on Substack Notes here. This hybrid-architecture trend with alternating attention and alt

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r on the open-weight market. It is developed by Zyphra, and one of the interesting details around the release is that the model was trained on AMD GPUs rather than the more common NVIDIA GPU (or Google TPU) setup. The main architecture detail, though, is Compressed Convolutional Attention (CCA), used together with grouped-query attention. Unlike MLA-style designs that mainly use a latent representation as a compact KV cache format, CCA performs the attention operation directly in the compressed

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ost memory, not device memory. Even though most of the inference engine artifacts are host-side, the setup process creates device resources that must be checkpointed and restored. Nvidia’s recent driver versions include an elegant solution to this problem. In short, the driver checkpoints device memory in host memory so that it can be checkpointed to disk by a host-side checkpointing system. Then, once the host-side system has restored the host memory, including the device checkpoint, the driver

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it runs continuously across every user query, agent step, and API call. And while training is a bounded investment, inference scales with every new user and use case you ship. At NVIDIA GTC 2026, NVIDIA CEO Jensen Huang framed this shift plainly: “People pay for information, but people mostly pay for work. Agentic systems get work done.” That shift from AI as a novelty to AI as a workhorse is exactly what’s reshaping infrastructure priorities. For Together AI, none of this is new. The inference

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tance and collaboration in resolving this issue: Robert Shaw (Red Hat, vLLM and llm-d Maintainer) Will Eaton (Red Hat, vLLM and llm-d Maintainer) Nicolò Lucchesi (Red Hat, vLLM and llm-d Maintainer) Mikhail Brinskii (NVIDIA, NIXL Maintainer) Leonid Genkin (NVIDIA, UCX Maintainer) Interested in tackling challenges like these? Join us at Mistral AI and help shape the future of AI infrastructure. We’re always looking for talented engineers and researchers to collaborate on cutting-edge projects. 0%

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saw on various social media platforms that people were pronouncing the team “dead” (as a one-hit wonder). I am sure the DeepSeek team has also been busy navigating the switch from NVIDIA to Huawei chips. By the way, I am not affiliated with them or have spoken with them; everything here is based on public information. As far as I know, they are back to using NVIDIA chips. Finally, it’s also not that they haven’t released anything. There have been a couple of smaller releases that trickled in thi

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