Weinan Hexin Completes Over 1 Billion Yuan C2 Round of Financing, Cumulative Financing of 3 Billion Yuan in Half a Year

ChipInside reported on October 28 that today, Hangzhou 3D compute-in-memory AI chip company Micro-Nano Core announced that it has recently completed a C2 round of financing exceeding 1 billion yuan.

This round of financing was led by Jiantou Investment, with co-investment from institutions including Hangzhou Capital, Kaitai Capital, Xiaochi Capital, Yantai Caijin, Shengkun Investment, Guotou Taikang, and Lingyang Fund, while several existing shareholders continued to increase their stakes. The funds from this round will be used for product development iteration and supply chain mass-production stocking, and the company plans to achieve large-scale commercialization and mass-production sales in the near term.

Combined with the C1 round completed in September this year, the company has completed more than 2 billion yuan in financing within two months, and a cumulative 3 billion yuan within half a year.

Micro-Nano Core was founded in 2021, is headquartered in Hangzhou, Zhejiang, and was incubated from the Zhejiang Provincial Peking University Institute of Information Technology. It focuses on compute-in-memory AI inference chips. The company says it has pioneered the world's first three-dimensional compute-in-memory 3D-CIM architecture, namely a fusion solution of "3D near-memory computing + SRAM compute-in-memory + RISC-V heterogeneous compute-in-memory," targeting large-model inference scenarios, while laying out both edge-side and cloud-side product lines.

The company's founder, chief scientist, and chairman Ye Le is an associate professor and doctoral supervisor at the School of Integrated Circuits of Peking University. His main research areas include compute-in-memory AI chips and architecture design, 3D integrated chips and architecture design, intelligent IoT AIoT chip design, and energy-efficient analog and mixed-signal integrated circuit design. He has published nearly 20 papers in top chip design journals such as ISSCC, JSSC, and TCAS-I.

▲Ye Le, founder, chief scientist, and chairman of Micro-Nano Core

According to the enterprise information query platform Qichacha, Micro-Nano Core has completed 9 rounds of financing since its establishment. In January this year, its B+ round of financing was completed, with GigaDevice participating; in June, the company received another B+ round of financing exceeding 100 million yuan, with institutions including Jiangcheng Fund, JiuKun Investment, SMIC Capital, BlueRun Ventures, and KaiFeng Ventures participating; in September, Micro-Nano Core's 1 billion yuan C1 round of financing was finalized, with investors including Yuanhao Investment, Jinfu Investment, Sunshine Insurance, and Yuanhe PuHua.

On the product side, Micro-Nano Core's 3D-CIM architecture integrates DRAM 3D near-memory computing, SRAM compute-in-memory, and RISC-V heterogeneous compute-in-memory, breaking through the memory wall and power wall of the von Neumann architecture at the architectural level.

According to the company's disclosures, multiple tape-out tests show that its SRAM compute-in-memory architecture chips can achieve 4-6 times higher compute density and 5-10 times higher energy efficiency than von Neumann architecture chips.

Micro-Nano Core's official website shows that the company has launched two major product lines, edge-side and cloud-side, based on CIM technology, both supporting cascading of multiple chips, achieving inference speeds of 150 to 300 tokens/s on the Llama series of models, focusing on high throughput and low power consumption, and broadly covering AI phones, AI PCs, IoT, and server scenarios.

Among them, the edge-side LP-CIM series integrates 2GB DRAM per chip, with INT8 computing power of no less than 20 TOPS, power consumption below 2W, using an LPDDR interface and supporting memory sharing; the cloud-side PCIe-CIM series integrates 2 to 12GB DRAM per chip, with INT8 computing power of 40 to 80 TOPS, power consumption below 4W, and uses a PCIe interface.

According to the company's disclosures, the cloud-side series can achieve compute density comparable to advanced processes based on mature processes, while greatly improving bandwidth and reducing power consumption.

Regarding mass-production progress, Micro-Nano Core disclosed that a total of three chips in the first-generation LP-CIM series and PCIe-CIM series have all been taped out, and are expected to be officially sent to customers for testing in early 2027 and to start volume supply.

In terms of commercialization, the company has completed the development of chips, boards/servers, and software stacks; on the edge side, it has carried out cooperation with multiple phone platforms, ODM manufacturers, and embodied intelligence companies, with some projects entering deep joint debugging; on the cloud side, it has been advancing computing solution evaluation and scenario-based POC testing with multiple CSP cloud service providers, AI Infra manufacturers, and AIDC computing service providers.

Conclusion: Compute-in-memory enters a commercialization window period

Micro-Nano Core's more than 2 billion yuan in financing within two months is not an isolated case when viewed against the overall heat of the compute-in-memory track: Jiutian Ruixin raised 1 billion yuan in half a year to bet on HBF, and Yizhu Technology recently also accumulated more than 1 billion yuan in financing, focusing on 3D DRAM compute-in-memory.

Various companies are laying out separately around different media such as SRAM, DRAM, and flash memory, and capital investment in compute-in-memory is moving from the conceptual stage into a commercialization window period.