TSMC's CoWoS Packaging Reportedly to Raise Prices 10% to 20%, AI Packaging and Testing Capacity Remains Tight

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On October 27, affected by the explosion in AI demand and comprehensive capacity tightness across the semiconductor supply chain, TSMC (TSM.US) plans to raise CoWoS packaging quotes by 10% to 20%.

This technology is widely used in high-end AI processors, and demand has extended from GPUs to server CPUs and custom ASICs. Longer AI chip testing cycles have intensified supply pressure on packaging and testing capacity, and chip equipment lead times have also lengthened from 3 to 6 months to 6 to 8 months. Downstream customers no longer have the time to bargain, saying that "as long as you can commit to a delivery date, we will place the order."

According to analyst estimates, TSMC's monthly CoWoS capacity is expected to exceed 130,000 wafers in 2026 and further increase to 200,000 wafers in 2027. TSMC Chairman C.C. Wei said that at this stage CoWoS remains customers' first choice, and TSMC is currently the only manufacturer to achieve mass production at the five-reticle scale. Its five-reticle-size packaging is already in mass production with excellent yield, and it continues to develop nine-reticle and fourteen-reticle-size solutions and advance CoPoS technology.

In addition, TSMC did not renegotiate prices for this year's annual equipment procurement and placed orders directly at the original prices, which indirectly indicates that current market demand is strong.

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