Cadence raises full-year revenue forecast and launches the Maestro model family for chip design

Cadence has diversified its revenue streams amid the expansion of agentic AI and physical AI. (Photo: Cadence)

PC본문_6월 Mouser (in Article)//

AD Manager | AD178089411676 //

// AD Manager | AD178089411676

Electronic design automation (EDA) company Cadence Design Systems expects artificial intelligence (AI) to make chip design up to 1,000 times more productive than in the past.

The company also outlined plans to integrate its own semiconductor design-specific AI models, alongside general-purpose AI models, into its EDA tools.

Cadence Chief Executive Officer Anirudh Devgan said during the company’s third-quarter earnings call on Oct. 26, local time, that IBM and Intel needed 500 engineers working for five years to design a single central processing unit (CPU) two decades ago, compared with 50 engineers working for six months today. Chip design has already become roughly 100 times easier, and AI could deliver an additional five- to tenfold efficiency gain, he said. Devgan expects the combined improvements to make chip design 1,000 times easier than it was 20 to 25 years ago.

Cadence unveiled Maestro, a family of AI models specialized for semiconductor and system design. The models are based on open-weight models post-trained using Cadence’s design tools and data. The system includes a router that selects between proprietary models and external frontier models depending on the design task. Cadence said initial results showed up to a 30% improvement in design quality and up to a fivefold improvement in token efficiency compared with general-purpose foundation models.

The strategy differs from that of rival Synopsys, which partnered with OpenAI to introduce GPT-Synopsys. Devgan said post-training frontier-class models, which was prohibitively expensive two years ago, can now be done at very little additional cost. He said controlling all three layers — models, agents and design tools — is essential to achieving the best results while protecting customer data confidentiality. Cadence plans to integrate Maestro with its AI design agents, including ChipStack, InnoStack and AuraStack.

The agents have already been deployed at major semiconductor companies. According to Devgan, Samsung Foundry adopted InnoStack in the third quarter and is using it to improve the efficiency of process migration and design technology co-optimization (DTCO). Renesas Electronics’ microcontroller unit (MCU) development team achieved a 34-fold productivity improvement by applying InnoStack to multiple tasks and plans to extend its use to layout automation. MediaTek integrated ChipStack into its production digital verification flow, increasing verification coverage by 50% to 70% while reducing engineering workloads by 1.4 to 2 times.

As chip design becomes easier, Cadence’s customer base is expanding. Devgan said about 45% of the company’s business comes from non-semiconductor companies. Hyperscalers, automotive companies, aerospace firms and financial institutions are increasingly designing their own chips.

Cadence also expects wider adoption of AI agents to drive greater use of existing EDA tools. Chief Financial Officer John Wall said agents can generate and run far more design iterations than engineers manually operating the tools, potentially driving a substantial increase in EDA tool consumption.

Cadence reported third-quarter revenue of $1.63331 billion, up 22% from a year earlier. Its non-GAAP operating margin, excluding one-time costs, was 44.1%, while non-GAAP earnings per share (EPS) rose 9% to $2.11. Backlog reached a record $8.2 billion at the end of the quarter.

The company raised its full-year revenue forecast to between $6.387 billion and $6.417 billion. The revised outlook implies 21% year-on-year growth, up from the 19% growth forecast issued with its second-quarter results.