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ZhidxUpdated Oct 25 21:57

Jiutian Ruixin completes a cumulative 1 billion yuan in financing over half a year, with participation from Meituan Strategic Investment, Xiaopeng Xinghang Capital and others

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Shenzhen-based compute-in-memory AI chip company Jiutian Ruixin announced that it has completed a cumulative 1 billion yuan in financing over half a year, with Yiwei Capital serving as financial advisor. Investors include Meituan Strategic Investment, Xinghang Capital under Xiaopeng Motors, Changcun Industrial Fund, Yuanhe PuHua, OmniVision Group, miHoYo Strategic Investment and others. The funds will be used for R&D and tape-out of HBF and SRAM compute-in-memory fusion chips, construction of the MPM software stack, and product and ecosystem deployment for cloud, edge and device. The company's ADA400 inference board delivers more than 2TB of capacity per card and more than 4TB/s of bandwidth, and on its in-development 3D fusion compute-in-memory chip engineering validation platform, DeepSeek-V4 achieves a decoding speed of about 20TPS in a "single card + 4 SSDs" configuration.

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The financing disclosure also presents Jiutian Ruixin's HBF and SRAM compute-in-memory roadmaps and product progress, offering insight into the pace at which compute-in-memory chips are being deployed in inference scenarios.

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On October 22, Silicon Insider reported that today, according to disclosure by Yiwei Capital, Shenzhen compute-in-memory AI chip company Jiutian Ruixin announced it has completed a cumulative 1 billion yuan in financing over half a year, with Yiwei Capital serving as financial advisor for this round. The related financing will be mainly used for the R&D and tape-out of HBF and SRAM compute-in-memory fusion chips, the construction of the MPM software stack, and product and ecosystem layout for cloud, edge, and device.

According to disclosure by Yiwei Capital, Jiutian Ruixin's investors include Meituan Strategic Investment, Xinghang Capital under XPeng Motors, Changcun Industrial Fund, Yuanhe Puhua, OmniVision Group, Zhiwei Capital, miHoYo Strategic Investment, and others, with existing shareholders Yinghao Capital and Weihao Chuangxin increasing their investment; the investors cover industry chain segments including storage, semiconductors, local life, smart vehicles, and digital content.

Founded in June 2018 and headquartered in Shenzhen, Jiutian Ruixin is an AI chip company centered on SRAM compute-in-memory chips, covering edge inference, device-cloud collaboration, and cloud large-model inference. The company takes MPM (Memory-Processor-Model) symbiotic design as its core methodology, and around SRAM compute-in-memory, high-bandwidth flash (HBF), and 3D vertical integration technologies, builds a product system from chips to servers.

The company's founder, chairman, and CEO Liu Hongjie graduated with a bachelor's degree in Electronic Science and Technology from Jilin University, obtained a master's degree in Integrated Circuit Design from Nanyang Technological University in Singapore, and later obtained a doctorate in Neurobionic Engineering from ETH Zurich in Switzerland, studying under Professor Tobi Delbruck, a pioneer in the field of neuromorphic sensory computing, and has long focused on neuromorphic computing and sensing-computing-memory integrated chip R&D.

▲ Jiutian Ruixin founder, chairman, and CEO Liu Hongjie

According to enterprise information query platform Qichacha, Jiutian Ruixin has completed multiple rounds of financing since its founding. In September 2025 it completed a B round of over 100 million yuan, invested by Yuanhe Puhua, Yinghao Capital, and others, with existing shareholders such as Weihao Chuangxin and MiraclePlus continuing to support. In January 2026 the company completed a B+ round, with participation from Shenzhen Futian Guidance Fund and others; in April of the same year, a B+ round of 120 million yuan, with investors including Will Semiconductor, China Merchants Zhiyuan Capital, Gettop Acoustic, and others.

In terms of products and technology, Jiutian Ruixin's two main technical lines are SRAM compute-in-memory and HBF. SRAM compute-in-memory completes high-frequency multiply-add operations inside the memory array, reducing the energy consumption and latency of weight movement; HBF organizes model weights and KV Cache closer to computation.

The company's products cover HBF SSD, the ADA300 series compute-in-memory chips, ADA400 inference boards, and AI inference servers. According to company disclosure, the ADA400 adopts a "left-brain/right-brain" heterogeneous architecture and wafer Chiplet integration, with single-card capacity exceeding 2TB and bandwidth exceeding 4TB/s, targeting inference for trillion-parameter models.

In terms of products under development, Jiutian Ruixin is developing a 3D fusion compute-in-memory chip that vertically stacks SRAM compute-in-memory with HBF; on the engineering validation platform, DeepSeek-V4 has achieved a decoding speed of about 20 TPS under a "single card + 4 SSD" configuration, and the HBF chip solution's design goal is to increase single-card bandwidth and TPS by more than 10 times, and single-machine performance by more than 100 times.

According to disclosure by Yiwei Capital, Jiutian Ruixin has become an Alpha partner enterprise in the HBF AI chip system of a leading manufacturer, its cloud computing power business is in contact with multiple internet manufacturers, its device-side computing power business has established cooperation with vivo, Honor, Lenovo, and others, and its compute-in-memory products have already been mass-produced and sold.

Currently, MoE has become the mainstream architecture for large models, with total model parameters entering the trillions, activating only a few experts per inference, and KV cache growing larger and larger. Facing the shift in the inference stage from "compute-limited" to "data-supply-limited," HBF has been introduced into view as a new storage tier.

HBM has limited single-card capacity and high cost, making it unrealistic to put all weights into it; ordinary SSD has sufficient capacity but low bandwidth and high latency, and if weights need to be repeatedly swapped in and out, inference will stall.

HBF exactly fills this layer, using flash memory to achieve scalable large capacity, and through high-parallel data paths and near-compute connections provides bandwidth close to that of compute units, allowing weights, expert parameters, and warm/cold KV cache to reside near computation, reducing the latency and power consumption of cross-tier data movement and also amortizing the overall cost of the inference system.

Conclusion: From minimal consensus to industry standard, HBF industrialization has just begun

Two years ago, HBF was still a minimal consensus, but at FMS 2026 this year, SK Hynix and SanDisk released the first HBF OCP specification, showing that HBF has officially moved from minimal consensus to an industry standard.

However, HBF industrialization is still in its early stages. The standard has just been established, and engineering validation and ecosystem building have only just begun; the pace of advancement by storage giants and the continued evolution of the HBM path will both affect the development pace of this route; at the same time, HBF's prospects are built on the assumption that the MoE architecture continues to become mainstream. If model architecture evolves and inference demand changes, HBF's applicability will also need to be re-examined.

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