三星在 JEDEC 论坛指出 AI 内存标准化面临挑战
Samsung Electronics Highlights Limits of AI Memory Standardization at JEDEC Forum < Semiconductor < 기사본문 - The Elec Inc.
三星电子在 2026 JEDEC 论坛上表示，LPDDR-PIM 与 zHBM 等下一代 AI 内存带有大量客户定制特性，令内存厂商在实际生产中极难管理。三星披露 LPDDR5X-PIM 内存带宽达常规 LPDDR5X 的 8 倍，AI 推理性能 102 TPS，约为 LPDDR5X 27 TPS 的 3.8 倍，较 8 月 Hot Chips 展示的 83 TPS 提升约 23%。其平均功耗 11.5 瓦，高于 LPDDR5X 的 8.4 瓦，但每瓦推理性能提升至 9 TPS/W。
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Samsung Electronics presents its LPDDR-PIM technology at the 2026 JEDEC Forum, held alongside SEDEX 2026 at COEX in Seoul on Oct. 15. (Photo: THE ELEC)
Samsung Electronics has acknowledged the challenges of standardizing next-generation artificial intelligence (AI) memory, as customer-specific designs extend beyond the base dies of high-bandwidth memory (HBM) into DRAM core dies, making them increasingly difficult for memory manufacturers to manage.
"LPDDR-based processing-in-memory (LPDDR-PIM) and z-high-bandwidth memory (zHBM) have many customer-specific features," said Hwang Ga-ram, a researcher on the product planning team of Samsung Electronics' Memory Business under its Device Solutions (DS) division, at the 2026 Joint Electron Device Engineering Council (JEDEC) Forum held alongside Semiconductor Exhibition (SEDEX) 2026 at COEX in Seoul on Oct. 15. "These features are extremely difficult for memory manufacturers to manage during actual production." Hwang added that other memory manufacturers likely face the same challenges.
Standards establish common specifications that allow different products to operate under the same requirements. Conventional DRAM has been manufactured according to such standards, but the integration of computing functions into DRAM has complicated the process. One example is LPDDR-PIM, which incorporates processing capabilities directly into low-power DRAM. Hwang expressed hope that the LPDDR6-PIM standard would be established by the end of this year.
Standardizing zHBM presents even greater challenges. Samsung's proposed zHBM architecture differs from conventional GPU packaging, which places a computing processor and HBM side by side on an interposer using 2.5-dimensional (2.5D) packaging. Instead, zHBM uses a three-dimensional (3D) stacked structure that directly connects HBM to the computing processor. Through-silicon vias (TSVs) are distributed throughout DRAM core dies to shorten data transfer distances. Because the memory connects directly to the processor, customized designs extend beyond the base die to the overall structure.
"Not every function can be fully standardized," Hwang said, while expressing hope that JEDEC member companies could cooperate to establish common standards.
Samsung also disclosed development results for its LPDDR5X-PIM technology. Its memory bandwidth is eight times that of conventional LPDDR5X, while AI inference performance reached 102 tokens per second (TPS), approximately 3.8 times the 27 TPS achieved by LPDDR5X. The result represents an improvement of about 23% over the 83 TPS demonstrated at Hot Chips in August.
Average power consumption was 11.5 watts, approximately 36% higher than the 8.4 watts consumed by LPDDR5X. However, inference performance per watt improved to 9 TPS/W, roughly 2.8 times the 3.2 TPS/W achieved by conventional LPDDR5X.
Lee Jun 2jun0504@thelec.kr
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