是德科技：AI 数据中心需端到端系统级验证以保障盈利能力

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Lee Sun-woo, president of Keysight Korea, speaks at a press conference. (Photo: THE ELEC)

Keysight has presented a system-level validation approach and solutions aimed at protecting the profitability of artificial intelligence (AI) data centers.

Lee Sun-woo, president of Keysight Korea, said at Keysight World Tech Day 2026 in Yangjae-dong, Seoul, on Oct. 21, "Even minor data transmission delays along communication paths connecting chips, memory, servers, racks and data centers can result in substantial capital losses." He added, "Beyond simply manufacturing high-performance individual semiconductors, companies must use system-level validation to completely eliminate data delays and bottlenecks in advance."

System-level validation integrates testing across the entire system lifecycle and its various layers, from chip design to chips, substrates, servers, racks, data centers and edge devices. It verifies and optimizes the operation of complex semiconductors and AI infrastructure under actual operating conditions. Conventional testing has primarily focused on measuring the performance of individual semiconductor chips or hardware components.

Lee cited Nvidia's latest graphics processing unit (GPU), Rubin, to illustrate the need for system-level validation. "Rubin is an expensive product capable of processing 9,000 words, or tokens, per second using AI models," he said. "However, if the high-bandwidth memory (HBM) inside an AI accelerator cannot supply the GPU with the data needed for AI computations quickly enough, the GPU will remain idle instead of utilizing its high computing capacity."

Preventing memory bottlenecks and other system-level delays requires validation at every stage, from chip design and board-level testing to servers and racks. Keysight has developed solutions covering all these stages.

For chip design, Keysight offers the W3650B Chiplet PHY Designer and W9100E 3D Interconnect Designer electronic design automation (EDA) tools. The W3650B is a simulator that verifies whether multiple chiplets communicate properly using standard interfaces. The W9100E calculates signal interference between interconnects in advanced semiconductor packaging technologies such as Intel's Embedded Multi-die Interconnect Bridge (EMIB), TSMC's Chip on Wafer on Substrate (CoWoS) and Samsung Electronics' H-Cube.

At the board integration stage, the XR8 oscilloscope and XA5 and XA6 signal analyzers can be used. The XR8 precisely measures signal distortion and noise in high-speed memory interfaces such as HBM and DDR5 after chips have been mounted on substrates. The signal analyzers use preselection to isolate target signals and filter out unwanted noise. The XA6 incorporates a GPU to increase wideband signal measurement speeds by up to 50 times.

For interconnect and server testing, Keysight offers its Functional Interconnect Test Solution (FITS) and XG7 Pro signal generator. FITS verifies bit error rates in 800G and 1.6T ultra-high-speed optical and copper cables, switches and transceivers. The XG7 Pro generates high-power, ultra-low-noise analog signals for testing communication devices.

At the rack and data center network level, Keysight provides KAI-DC Builder software, which reproduces data transmission delays caused by network congestion in a virtual environment. Its AresONE Plus 1600GE test platform validates high-density data traffic handled by network hardware such as switches.

Keysight also offers KAI-IB, an emulator that generates simulated AI inference traffic to diagnose GPU idle time and bottlenecks, and CyPerf software, which measures cybersecurity performance and processing capabilities at higher application layers.

JEONG IL JOO 1week@thelec.kr

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