长鑫存储称 4F² 存储架构取得突破，计划 2026 年底前推出服务器内存
China’s CXMT Claims Memory Breakthrough, Challenging Samsung and SK Hynix
长鑫存储（CXMT）总裁曹堪宇在上海一场行业会议上称，公司已开发出 4F² 存储单元架构，可将单元占位面积从传统 6F² 的六倍特征尺寸平方缩减至四倍，并计划在 2026 年底前推出基于该架构的服务器内存产品。该架构采用垂直环栅（Vertical Surrounding Gate）方案，用于降低漏电等微缩难题。此前长鑫已宣布第五代 DRAM 平台 G5 量产，并推出 24-gigabit LPDDR5X 芯片，称其有源区半间距为 11.95 纳米、每片晶圆产出裸片比上一代多至少 50%；同月还宣布 LPDDR6 量产，首发于小米 18 Fold。长鑫 7 月上海 IPO 募资约 86 亿美元，第二季度全球 DRAM 营收份额达 9.5%，但在 HBM 领域仍落后于三星和 SK 海力士。
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ChangXin Memory Technologies (CXMT), China’s largest domestic DRAM maker, claims to have developed a memory-cell architecture that could pack more data into less silicon than existing designs, potentially challenging Samsung Electronics and SK Hynix.
The company plans to launch a new server-memory product based on the 4F² architecture before the end of 2026, CXMT President Cao Kanyu said at a recent industry conference in Shanghai, as reported by Bloomberg.
If the architecture achieves commercially viable production yields, it could narrow the gap with South Korea’s memory manufacturers, which have explored similar designs for years.
Conventional 6F² DRAM architecture uses a memory-cell footprint equivalent to six times the square of the minimum feature size. However, a 4F² design reduces that footprint to four times the square, potentially increasing memory density and lowering manufacturing costs.
CXMT said it is using a Vertical Surrounding Gate approach that changes how transistors are arranged to reduce electrical leakage and other problems associated with further miniaturisation.
The announcement comes as CXMT advances across several memory categories.
Last month, the company announced mass production of its fifth-generation DRAM platform, known as G5, and introduced 24-gigabit LPDDR5X chips built on the process. CXMT said the platform achieves an 11.95-nanometre active-area half-pitch and produces at least 50% more dies—single rectangle of silicon—per wafer than its predecessor.
Earlier that month, CXMT announced mass production of LPDDR6 memory, with the chips making their commercial debut in Xiaomi’s 18 Fold flagship smartphone. The company claims peak data rates of 12,800 megabits per second, alongside up to 60% higher bandwidth and 20% lower power consumption than the previous generation of LPDDR5X, based on its internal testing
CXMT’s progress is putting pressure on an already competitive memory market, where AI data centre demand has driven up prices and pushed manufacturers to expand capacity.
The company raised approximately $8.6 billion in its July Shanghai IPO, and its share of global DRAM revenue reached 9.5% in the second quarter. However, it still lags behind leading manufacturers like Samsung and SK Hynix in high-bandwidth memory (HBM), which powers AI accelerators.
On October 13, Samsung and SK Hynix shares fell more than 7% in South Korea, while Micron also declined in US trading. Bloomberg attributed the sell-off partly to investor reaction to CXMT’s announcement, although concerns about AI investment returns also weighed on semiconductor stocks.