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Japanese team publishes paper on slow-light silicon photonic modulator

1 reports1 story updatesUpdated Oct 23 14:00

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A team composed of Yokohama National University, Institute of Science Tokyo, the National Institute of Advanced Industrial Science and Technology (AIST), and the Photonics Electronics Technology Research Association (PETRA) published a paper on a silicon photonic modulator utilizing the slow-light effect. According to a report dated October 23, 2026, the team published results in Nature Communications: by etching nanoscale microholes in a silicon photonic crystal waveguide to slow light and incorporating a built-in electro-optic equalizer to compensate bandwidth, they achieved a single-channel rate of 200 Gb/s with energy consumption of only 26 femtojoules per bit. The device length is 320 micrometers, achieving 140 Gb/s in OOK format and 200 Gb/s with PAM-4, with a volume about an order of magnitude smaller than conventional MZMs, and it can be manufactured using CMOS-compatible processes. The report states that this architecture is expected to be used in co-packaged optics, but current optical insertion loss is relatively high, and mass production still awaits loss optimization and yield verification.

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A team from Yokohama National University and others achieves 200Gb/s and 26 femtojoules per bit using a slow-light silicon photonic modulator

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Oct 23

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    A team from Yokohama National University and others achieves 200Gb/s and 26 femtojoules per bit using a slow-light silicon photonic modulator

    A team from Yokohama National University, Institute of Science Tokyo, AIST, and PETRA published in Nature Communications a slow-light silicon photonic modulator that slows light by etching nanoscale micro-holes in a silicon photonic crystal waveguide and incorporates a built-in electro-optic equalizer to compensate bandwidth, achieving a single-channel rate of 200Gb/s with energy consumption of only 26 femtojoules per bit. The device is 320 micrometers long, delivers 140Gb/s in OOK format and 200Gb/s with PAM-4, is about an order of magnitude smaller than conventional MZMs, and can be manufactured using CMOS-compatible processes. This architecture is expected to be used in co-packaged optics, but current optical insertion loss is relatively high, and mass production still awaits loss optimization and yield verification.

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