CEVA 发布第二代 NeuPro NPU，AI 吞吐量翻倍

CEVA unveils its second-generation NeuPro NPU product lineup, designed to double AI processing throughput and enhance energy efficiency across applications from edge devices to data centers. (Photo: CEVA)

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CEVA unveiled its second-generation NeuPro neural processing unit (NPU) product lineup on Nov. 2.

The second-generation lineup delivers up to twice the artificial intelligence (AI) processing throughput per square millimeter compared with the first generation, while energy efficiency has improved by 50%.

CEVA plans to expand its business into AI infrastructure, including AI inference semiconductors, intelligent memory, and connectivity chips, using the new product family. The lineup is currently available to select customers for early access, with full production supply scheduled to begin in the second quarter of 2027.

More than 15 customers have licensed the first-generation NeuPro. Through collaboration with these customers, CEVA identified the relative importance of computing performance, memory bandwidth, power consumption, and cost based on intended AI applications. The new lineup therefore offers multiple computing engines designed for applications ranging from always-on, low-power sensors and edge devices to data centers and other AI infrastructure.

All products in the lineup use the same instruction set architecture (ISA) and a common software development kit (SDK). This allows customers to reuse existing software assets when designing systems that integrate multiple NPUs into a single system-on-chip (SoC).

The next-generation NeuPro lineup supports workloads ranging from basic object recognition and classification to transformer-based large language models (LLMs), multimodal AI that understands text, speech, and images, agentic AI that makes decisions and takes actions autonomously, and Physical AI. It also supports FP4 and FP8 floating-point formats, along with mixed-precision computing, allowing AI processing precision to be flexibly reduced to improve efficiency.

The architecture reduces memory usage and the volume of data transferred within and between chips. It adds a paged key-value (KV) cache feature, which manages memory in separate blocks as conversational context grows, and a dynamic tensor shape feature that handles frequently changing input data formats, such as prompts, without performance degradation or memory waste. Tensor reshaping also improves utilization of the chip's multiply-accumulate (MAC) units.

For large AI models, the architecture supports a Mixture-of-Experts (MoE) structure, which selectively activates expert computing models suited to specific queries, and a linear attention structure designed to analyze long sequences more efficiently.